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Volumn 16, Issue 6, 1997, Pages 587-596

Postlayout logic restructuring using alternative wires

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FLOWCHARTING; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

EID: 0031153009     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.640617     Document Type: Article
Times cited : (47)

References (13)
  • 1
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    • 0028259317 scopus 로고    scopus 로고
    • FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
    • vol. 13, pp. 1-12, Jan. 1994.
    • J. Cong and Y. DingFlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs, IEEE Trans. Computer-Aided Design, vol. 13, pp. 1-12, Jan. 1994.
    • IEEE Trans. Computer-Aided Design
    • Cong, J.1    Ding, Y.2
  • 7
    • 0026175524 scopus 로고    scopus 로고
    • Chortle-erf: Fast technology mapping for lookup table-based FPGA's
    • 28th Design Automation Conf., June 1991, pp. 227-233.
    • R. J. Francis, J. Rose, and Z. VranesicChortle-erf: Fast technology mapping for lookup table-based FPGA's, in Proc. 28th Design Automation Conf., June 1991, pp. 227-233.
    • Proc.
    • Francis, R.J.1    Rose, J.2    Vranesic, Z.3
  • 8
    • 0023211128 scopus 로고    scopus 로고
    • A topological search algorithm for ATPG
    • 24th Design Automation Conf., June 1987, pp. 502-508.
    • T. Kirkland and M. R. MercerA topological search algorithm for ATPG, in Proc. 24th Design Automation Conf., June 1987, pp. 502-508.
    • Proc.
    • Kirkland, T.1    Mercer, M.R.2
  • 9
    • 84961249468 scopus 로고    scopus 로고
    • Recursive learning: An attractive alternative to the decision tree for test generation digital circuits
    • 1992, pp. 816-825.
    • W. Kunz and D. K. PradhanRecursive learning: An attractive alternative to the decision tree for test generation digital circuits, in Proc. Int. Test Conf., Oct. 1992, pp. 816-825.
    • Proc. Int. Test Conf., Oct.
    • Kunz, W.1    Pradhan, D.K.2
  • 10
    • 0027062422 scopus 로고    scopus 로고
    • Improved logic synthesis algorithms for table look up architectures
    • R. K. Brayton, and A. Sangiovanni Vincentelli 1991, pp. 564-576.
    • R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni VincentelliImproved logic synthesis algorithms for table look up architectures, in Proc. Int. Conf. Computer-Aided Design, Nov. 1991, pp. 564-576.
    • Proc. Int. Conf. Computer-Aided Design, Nov.
    • Murgai, R.1    Shenoy, N.2
  • 11
    • 0024753283 scopus 로고    scopus 로고
    • The transduction method-design of logic networks based on permissible functions
    • 1404-1424, Oct. 1989.
    • S. Muroga, Y. Kambayshi, H. C. Lai, and J. N. CullineyThe transduction method-design of logic networks based on permissible functions, IEEE Trans. Comput., pp. 1404-1424, Oct. 1989.
    • IEEE Trans. Comput., Pp.
    • Muroga, S.1    Kambayshi, Y.2    Lai, H.C.3    Culliney, J.N.4
  • 12
    • 0024137442 scopus 로고    scopus 로고
    • Advanced automatic test pattern generation and redundancy identification techniques
    • 1988, pp. 30-34.
    • M. Schulz and E. AuthAdvanced automatic test pattern generation and redundancy identification techniques, in Proc. Fault Tolerant Computing Symp., June 1988, pp. 30-34.
    • Proc. Fault Tolerant Computing Symp., June
    • Schulz, M.1    Auth, E.2
  • 13
    • 0026175523 scopus 로고    scopus 로고
    • A heuristic method for FPGA technology mapping based on the edge visibility
    • 28th Design Automation Conf., 1991, pp. 248-251.
    • N.-S. WooA heuristic method for FPGA technology mapping based on the edge visibility, in Proc. 28th Design Automation Conf., 1991, pp. 248-251.
    • Proc.
    • Woo, N.-S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.