SPFD-based global rewiring

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2002, Pages 77-84

  Cong, Jason ^a   Lin, Yizhou ^a   Long, Wangning ^a  

^a University of California   (United States)

Author keywords

FPGA synthesis; Logical re synthesis; SPFD; SPFD based global rewiring

Indexed keywords

ALGORITHMS; ELECTRIC WIRING; LOGIC DESIGN; PROBLEM SOLVING; THEOREM PROVING;

AUTOMATIC TEST PATTERN GENERATION (ATPG);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0036385607     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/503057.503060     Document Type: Conference Paper

References (22)

1. Altera, Quartus II Software Overview, http://www.altera.com/products/software/quartus2/qts-index.html.
2. L.A. Entrena and K.-T. Cheng. Combinational and Sequential Logic Optimization by Redundancy Addition and Removal. IEEE Transaction on CAD of ICS, Vol. 14, No. 7, pp. 909-916, July 1995.
3. R. K. Brayton. Understanding SPFDs: A New Method for Specifying Flexibility. In International Workshop on Logic Synthesis, 1997.
4. C.-W. Chang, C.-K. Cheng, P. Suaris, and M. Marek-Sadowska. Fast Post-placement Rewiring Using Easily Detectable Functional Symmetries. In Design Automation Conference, p. 286-289, 2000.
5. S.-C. Chang, M Marek-Sadowska, and K-T Cheng. Perturb and Simplify: Multilevel Boolean Network Optimizer. IEEE Trans CAD of ICAS, Vol. 15, No. 12, Dec 1996, pp. 1494 - 1504.
6. S.-C. Chang, K.-T. Cheng, N.-S. Woo, and M. Marek-Sadowska. Postlayout rewiring using alternative wires. IEEE Transaction on CAD of ICS, Vol. 16, No.6, p.587-96, June 1997.
7. S.-C. Chang, L. V. Ginneken, and M. Marek-Sadowska. Circuit Optimization by Rewiring. IEEE Transaction on Computers, Vol. 48, No. 9, pp. 962-970 September 1999.
8. P. Chong, Y. Jiang, S. Khatri, F. Mo, S. Sinha, and R. Brayton. Don't Care Wires in Logical/Physical Design. In International Workshop on Logic Synthesis, pp. 1- 9, 2000.
9. J. Cong, Y. Hwang. Simultaneous Depth and Area Minimization in LUT-Based FPGA Mapping. Proc. ACM 3rd Int'l Symp. on FPGA, Feb. 1995, pp. 68-74.
10. J. Cong, S. K. Lim. Edge Separability based Circuit Clustering With Application to Circuit Partitioning. IEEE/ACM Asia South Pacific Design Automation Conference, p. 429-434, 2000.
11. J. Cong, J. Peck, and Y. Ding. RASP: A General Logic Synthesis System for SRAM-based FPGAs. In Proc. ACM/SIGDA Int'l Symp. on FPGAs, p. 137-143, Feb. 1996.
12. R. Huang, Y. Wang, and K.-T. Cheng. LIBRA-a library-independent framework for post-layout performance optimization. In International Symposium on Physical Design, p.135-140, 1998.
13. J. - M. Hwang, F. - Y. Chiang, and T.- T. Hwang. A Re-engineering Approach to Low Power FPGA Design Using SPFD. In Design Automation Conference, p.722-725, 1998.
14. Y.-M. Jiang, A. Krstic, K.-T. Cheng, and M. Marek-Sadowska. Post-layout rewiring for performance optimization. In Design Automation Conference, p.662-665, 1997.
15. W. Kurtz and P. R. Menon. Multilevel Logic optimization by implication Analysis", In International Conference on Computer Aided Design, p. 6-13.
16. E. Sentovich, et. al. SIS: A System for Sequential Circuit Synthesis. Memorandum No. UCB/ERL M92/41, Dept. EECS, UC Berkeley, 1992.
17. S. Sinha and R. K. Brayton. Implementation and Use of SPFDs in Optimizing Boolean Networks. In International Conference on Computer Aided Design, p. 103 - 110, 1998.
18. Fabio Somenzi. CUDD: CU Decision Diagram Package Release 2.3.0. Technique Report, Dept. of ECE, Univ. of Colorado at Boulder, 1998.
19. S. Yamashita, H. Sawada and A. Nagoya. A New Method to Express Functional Permissibilities for LUT based FPGAs and Its Applications. In International Conference on Computer Aided Design, p. 254 - 261, 1996.
20. Y. Wu, W. Long, and H. Fan. A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks. In IEEE 13th International Conference on VLSI Design (VLSI Design 2000), p.268-73, Jan. 2000.
21. K.C. Chen, J. Cong, Y. Ding, A. Kahng, and P. Trajmar. DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. In IEEE Design & Test, pp. 7-20, September, 1992.
22. J. Cong, Y. Lin, W. Long. SPFD-based Global Rewiring. In UCLA CSD Tech. Report. No.010043. Dec. 2001.