Using simulation and satisfiability to compute flexibilities in Boolean networks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 5, 2006, Pages 743-754

  Mishchenko, Alan ^a,b,e   Zhang, Jin S ^a,c   Sinha, Subarna ^d   Burch, Jerry R ^a,d   Brayton, Robert ^a,b,f,g   Chrzanowska Jeske, Malgorzata ^a,c,f,h,i  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Portland State University   (United States)

^d SYNOPSYS INC   (United States)

^e UNIVERSITY OF CALIFORNIA   (United States)

^f Synopsys Inc ^*  (United States)

^g NATIONAL ACADEMY OF ENGINEERING   (United States)

^h ACM   (United States)

ⁱ VLSI Systems and Applications   (United States)

Author keywords

Boolean network; Logic synthesis; Satisfiability; Simulation

Indexed keywords

BOOLEAN NETWORK; COMPUTATION ENGINE; LOGIC SYNTHESIS; SATISFIABILITY;

BINARY SEQUENCES; COMPUTATION THEORY; COMPUTER NETWORKS; COMPUTER SIMULATION; DECISION THEORY;

BOOLEAN ALGEBRA;

EID: 33646385935     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.860955     Document Type: Conference Paper

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