Performance optimization by interacting netlist transformations and placement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 19, Issue 3, 2000, Pages 350-358

  Stenz, Guenter ^a   Riess, Bernhard M ^a   Rohfleisch, Bernhard ^a   Johannes, Frank M ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; DELAY CIRCUITS; ELECTRIC NETWORK SYNTHESIS; MATHEMATICAL MODELS; OPTIMIZATION; VLSI CIRCUITS;

INTERCONNECT; NETLIST PLACEMENT; NETLIST TRANSFORMATIONS; POST LAYOUT SYNTHESIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034157131     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.833203     Document Type: Article

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