Portless SRAM - A high-performance alternative to the 6T methodology

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 11, 2007, Pages 2600-2610

  Wieckowski, Michael ^a,b   Patil, Sandeep ^a   Margala, Martin ^c  

^a University of Rochester   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

^c University of Massachusetts   (United States)

Author keywords

5T; 6T; CMOS memory; Low power; SRAM

Indexed keywords

5T; 6T; CMOS MEMORY; LOW POWER; SRAM;

SEMICONDUCTOR STORAGE;

STATIC RANDOM ACCESS STORAGE;

EID: 51749104874     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.907173     Document Type: Conference Paper

References (25)

1. J. D. Schmidt, "Integrated MOS random-access memory," Solid-State Design, pp. 21-25, 1965.
2. K. Takeda, Y. Aimoto, N. Nakamura, H. Toyoshima, T. Iwasaki, K. Noda, K. Matsui, S. Itoh, S. Masuoka, T. Horiuchi, A. Nakagawa, K. Shimogawa, and H. Takahashi, "A 16 Mb 400 MHz loadless CMOS four-transistor SRAM macro," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2000, pp. 264-265.
3. B.Wang and J. B. Kuo, "A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability," in Proc. 2000 IEEE ISCAS, Geneva, Switzerland, 2000, vol. 5, pp. 733-736.
4. I. Carlson, S. Andersson, S. Natarajan, and A. Alvandpour, "A high density, low leakage, 5T SRAM for embedded caches," in Proc. 30th Eur. Solid-State Circuits Conf., Leuven, Belgium, 2004, pp. 215-218.
5. R. E. Aly, M. I. Faisal, and M. A. Bayoumi, "Novel 7T sram cell for low power cache design," in Proc. IEEE Int. SOC Conf., Herndon, VA, 2005, pp. 171-174.
6. K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Kobatake, "A read-static-noise-margin-free SRAM cell for low-Vdd and high-speed applications," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 113-121, Jan. 2006.
7. M. M. Khellah and M. I. Elmasry, "A low-power high-performance current-mode multiport SRAM," IEEE Trans. Very Large Scale Integrat. (VLSI) Syst., vol. 9, no. 5, pp. 590-598, Oct. 2001.
8. M. Wieckowski and M. Margala, "A novel five-transistor (5T) SRAM cell for high performance cache," in Proc. IEEE Int. SOC Conf., 2005, pp. 101-102.
9. K. Agarwal and S. Nassif, "Statistical analysis of SRAM cell stability," in Proc. 43rd ACM/IEEE Design Automation Conf., San Francisco, CA, 2006, pp. 57-62.
10. E. Seevinck, F. List, and J. Lohstroh, "Static noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 748-754, Oct. 1987.
11. J. Lohstroh, E. Seevinck, and J. de Groot, "Worst-case static noise margin criteria for logic circuits and their mathematical equivalence," IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 803-807, Dec. 1983.
12. R. W. Mann, W. W. Abadeer, M. J. Breitwisch, O. Bula, J. S. Brown, and B. C. Colwill, "Ultralow-power SRAM technology," IBM J. Res. Dev., vol. 47, pp. 553-566, Sep./Nov. 2003.
13. C. H. Kim, K. Jae-Joon, S. Mukhopadhyay, and K. Roy, "A forward body-biased low-leakage SRAM cache: Device, circuit and architecture considerations," IEEE Trans. Very Large Scale Integrat. (VLSI) Syst., vol. 13, no. 3, pp. 349-357, Mar. 2005.
14. P. Elakkumanan, C. Thondapu, and R. Sridhar, "DG-SRAM: A low leakage memory circuit," in Proc. IEEE Int. SOC Conf., 2005, pp. 167-170.
15. K. Kanda, K. Sadaaki, and T. Sakurai, "90% write power-saving SRAM using sense-amplifying memory cell," IEEE J. Solid State Circuits, vol. 39, no. 6, pp. 927-933, Jun. 2004.
16. K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda, "A bitline leakage compensation scheme for low-voltage SRAMs," IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 726-734, May 2001.
17. Y. Ye, M. Khellah, D. Somasekhar, A. Farhang, and V. De, "A 6-GHz 16-kb L1 cache in a 100-nm dual-Vt technology using a bitline leakage reduction (BLR) technique," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 839-842, May 2003.
18. K. N. Sung, K. Flautner, D. Blaauw, and T. Mudge, "Circuit and microarchitectural techniques for reducing cache leakage power," IEEE Trans. Very Large Scale Integrat. (VLSI) Syst., vol. 12, pp. 167-184, 2004.
19. F. Frustaci, P. Corsonello, S. Perri, and G. Cocorullo, "Techniques for leakage energy reduction in deep submicrometer cache memories," IEEE Trans. Very Large Scale Integrat. (VLSI) Syst., vol. 14, no. 11, pp. 1238-1249, Nov. 2006.
20. D. Ji-Seong, K. Dae-Wook, L. Sang-Hoon, L. Jong-Bae, P. Youngkwan, Y. Moon-Hyun, and K. Jeong-Taek, "A unified statistical model for inter-die and intra-die process variation," in Proc. Int. Conf. Simulation Semicond. Processes Devices, 2005, pp. 131-134.
21. R. Venkatraman, R. Castagnetti, and S. Ramesh, "The statistics of device variations and its impact on SRAM bitcell performance, leakage and stability," in Proc. 7th Int. Symp. Quality Electronics Design, San Jose, CA, 2006, p. 6.
22. R. Heald and P. Wang, "Variability in sub-100 nm SRAM designs," in Proc. Int. Conf. Computer-Aided Design, 2004, pp. 347-352.
23. B. S. Amrutur and M. A. Horowitz, "Fast low-power decoders for RAMs," IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1506-1515, Oct. 2001
24. P. Y. Chee, P. C. Liu, and L. Siek, Electron. Lett. "High-speed hybrid current-mode sense amplifier for CMOS SRAMs," Apr. 1992, vol. 28, no. 9, pp. 871-873.
25. R. V. Joshi, S. P. Kowalczyk, Y. H. Chan, W. V. Huott, S. C. Wilson, and G. J. Scharff, "A 2 GHz cycle, 430 ps access time 34 kb L1 directory SRAM in 1.5 V, 0.18 -m CMOS bulk technology," in Symp. VLSI Circuits Dig. Tech. Papers, 2000, pp. 222-225.