A forward body-biased low-leakage SRAM cache: Device, circuit and architecture considerations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 3, 2005, Pages 349-357

  Kim, Chris Hyung Il ^a   Kim, Jae Joon ^b   Mukhopadhyay, Saibal ^c   Roy, Kaushik ^c  

^a UNIVERSITY OF MINNESOTA   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c PURDUE UNIVERSITY   (United States)

Author keywords

Forward body biasing (FBB); Halo doping; Leakage power; SRAM; Super high Vt

Indexed keywords

CACHE MEMORY; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; OPTIMIZATION; SEMICONDUCTOR DOPING; TRANSISTORS;

FORWARD BODY BIASING (FBB); HALO DOPING; LEAKAGE POWER; SUPER HIGH VT;

STATIC RANDOM ACCESS STORAGE;

EID: 15844361963     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.842903     Document Type: Article

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