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Volumn 2005, Issue , 2005, Pages 131-134

A unified statistical model for inter-die and intra-die process variation

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CORRELATION METHODS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENTS; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); SENSITIVITY ANALYSIS; THRESHOLD VOLTAGE;

EID: 33747043896     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (18)

References (9)
  • 1
    • 0032272376 scopus 로고    scopus 로고
    • Within-chip variability analysis
    • Dec.
    • Sani R.Nassif, "Within-Chip Variability Analysis," in Proc. IEDM, Dec. 1998.
    • (1998) Proc. IEDM
    • Nassif, S.R.1
  • 2
    • 33845880754 scopus 로고    scopus 로고
    • Impact of within-die parameter fluctuations on future maximum clock
    • May
    • K. A. Bowman, and J. D. Meindl, "Impact of within-die parameter fluctuations on future maximum clock," in Proc. CICC, May 2001.
    • (2001) Proc. CICC
    • Bowman, K.A.1    Meindl, J.D.2
  • 4
    • 84954420400 scopus 로고    scopus 로고
    • A statistical gate delay model for intra-chip and inter-chip variabilities
    • Jan.
    • K. Okada, K. Yamaoka, and H. Onodera, "A statistical gate delay model for intra-chip and inter-chip variabilities" in Proc. DAC, Jan. 2003.
    • (2003) Proc. DAC
    • Okada, K.1    Yamaoka, K.2    Onodera, H.3
  • 5
    • 0036575868 scopus 로고    scopus 로고
    • Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits
    • May
    • M. Orshansky, L. Milor, Pinhong Chen, K. Keutzer, and Chenming Hu, "Impact of spatial Intrachip gate Length Variability on the Performance of High-Speed Digital Circuits," IEEE Trans. Computer-Aided Design, Vol.21, NO.5, May 2002.
    • (2002) IEEE Trans. Computer-aided Design , vol.21 , Issue.5
    • Orshansky, M.1    Milor, L.2    Chen, P.3    Keutzer, K.4    Hu, C.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.