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Volumn , Issue , 2005, Pages 167-170

DG-SRAM: A low leakage memory circuit

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED MEMORIES; GATE LEAKAGE; GATE TUNNELING CURRENT; OXIDE THICKNESS;

EID: 30844469301     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (2)

References (12)
  • 4
    • 2942676776 scopus 로고    scopus 로고
    • Overcoming timing, power bottlenecks
    • April
    • J. Abraham, "Overcoming timing, power bottlenecks," EE Times, p. 58, April 2003.
    • (2003) EE Times , pp. 58
    • Abraham, J.1
  • 7
    • 0034453378 scopus 로고    scopus 로고
    • CMOS device optimization for system-on-a- Chip applications
    • K. Imai et al., "CMOS device optimization for system-on-a- chip applications," in IEDM Technical Digest, pp. 445-458, 2000.
    • (2000) IEDM Technical Digest , pp. 445-458
    • Imai, K.1
  • 8
    • 14244267091 scopus 로고    scopus 로고
    • Online
    • UC Berkeley Device Group, "Berkeley Predictive Technology Model." Online, http://www-devices.eecs.berkeley.edu/ptm, 2000.
    • (2000) Berkeley Predictive Technology Model
  • 9
    • 0034453479 scopus 로고    scopus 로고
    • BSIM4 gate leakage model including source-drain partition
    • December
    • K. M. Cao et al., "BSIM4 gate leakage model including source-drain partition," in IEEE IEDM Technical Digest, pp. 815-818, December 2000.
    • (2000) IEEE IEDM Technical Digest , pp. 815-818
    • Cao, K.M.1
  • 10
    • 0037321205 scopus 로고    scopus 로고
    • A single-Vt low-leakage gated-ground cache for deep submicron
    • February
    • A. Agarwal, H. Li, and K. Roy, "A single-Vt Low-Leakage gated-ground Cache for Deep Submicron," in IEEE Journal of Solid-State Circuits, pp. 319-328, February 2003.
    • (2003) IEEE Journal of Solid-state Circuits , pp. 319-328
    • Agarwal, A.1    Li, H.2    Roy, K.3
  • 12
    • 0035308547 scopus 로고    scopus 로고
    • The impact of instrinsic device fluctuations on CMOS SRAM cell stability
    • April
    • A. Bhavanagarwala, X. Tang, and J. Meindl, "The impact of instrinsic device fluctuations on CMOS SRAM cell stability," in IEEE Journal of Solid-State Circuits, pp. 658-665, April 2001.
    • (2001) IEEE Journal of Solid-state Circuits , pp. 658-665
    • Bhavanagarwala, A.1    Tang, X.2    Meindl, J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.