A novel five-transistor (5T) sram cell for high performance cache

Proceedings - IEEE International SOC Conference

Volumn , Issue , 2005, Pages 101-102

  Wieckowski, Michael ^a   Margala, Martin ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT;

FIVE-TRANSISTOR (5T) SRAM CELL;

STATIC RANDOM ACCESS STORAGE;

EID: 30844457740     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. K. Nii et. al., "A 90-nm Low-Power 32-kB Embedded SRAM With Gate Leakage Supression Circuit for Mobile Applications," IEEE Journal of Solid-State Circuits, Vol. 39, No. 4, April 2004, Pages: 684-693.
2. N. Azizi, A. Moshovos, F. N. Najm, "Low-Leakage Asymmetric-Cell SRAM," ISLPED, August 2002.
3. T. Douseki, N. Shibata, J. Yamada, "A 0.5-1 V MTCMOS/SIMOX SRAM macro with multi-Vth memory cells," SOI Conference, 2000 IEEE International, 2-5 Oct. 2000, Pages:24-25.
4. C. Lage, J.D. Hayden, C. Subramanian, "Advanced SRAM Technology - The Race between 4T and 6T Cells," in Electron Devices Meeting, 1996, International, 8-11 Dec. 1996, Pages: 271-274.
5. M.M. Khellah, M.I. Elmasry, "A low-power high-performance current-mode multiport SRAM," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Volume: 9, Issue: 5, Oct. 2001 Pages: 590-598.
6. Carlson, I. Andersson, S. Natarajan, A. Alvandpour, "A high density, low leakage, 5T SRAM for embedded caches," Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, 21-23 Sept. 2004, Pages: 215-218.
7. R.W. Mann et. al., "Ultralow-power SRAM Technology," IBM Journal of Research and Development, Volume: 47, Number: 5/6, Sept./Nov. 2003, Pages: 553-566.