A 16Mb 400MHz loadless CMOS four-transistor SRAM macro

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 264-265

  Takeda, K ^a   Aimoto, Y ^a   Nakamura, N ^a   Toyoshima, H ^a   Iwasaki, T ^a   Noda, K ^a   Matsui, K ^a   Itoh, S ^a   Masuoka, S ^a   Horiuchi, T ^a   Nakagawa, A ^a   Shimogawa, K ^a   Takahashi, H ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; MOSFET DEVICES; SPURIOUS SIGNAL NOISE;

DUAL-PULSE DRIVERS (DPD);

STATIC RANDOM ACCESS STORAGE;

EID: 0034431135     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. 2 loadless CMOS four-transistor SRAM cell in a 0.18μm logic technology
2. A 1.4ns access 700MHz 288Kb SRAM macro with expandable architecture