The statistics of device variations and its impact on SRAM bitcell performance, leakage and stability

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 190-195

  Venkatraman, R ^a   Castagnetti, R ^a   Ramesh, S ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BITLINE LEAKAGES; CMOS TECHNOLOGY; DEVICE VARIATIONS; ELECTRICAL PERFORMANCE; ELECTRICAL TESTS; MEMORY ARRAY; SRAM BIT CELL; SRAM DESIGN;

CMOS INTEGRATED CIRCUITS; LOGIC DESIGN;

STATIC RANDOM ACCESS STORAGE;

EID: 84886737474     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.134     Document Type: Conference Paper

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