A bitline leakage compensation scheme for low-voltage SRAMs

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 5, 2001, Pages 726-734

  Agawa, Ken'ichi ^b   Hara, Hiroyuki ^b   Takayanagi, Toshinari ^b   Kuroda, Tadahiro ^a,c  

^a IEEE

^b TOSHIBA CORPORATION   (Japan)

^c KEIO UNIVERSITY   (Japan)

Author keywords

Bitline leakage currents; CMOS analog integrated circuits; Compensation scheme; Leak detection; Low voltage operation; SRAM chips

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; THRESHOLD VOLTAGE; TRANSISTORS;

BITLINE LEAKAGE COMPENSATION; BITLINE LEAKAGE CURRENTS; LOW VOLTAGE OPERATION; TRANSMISSION TRANSISTOR;

RANDOM ACCESS STORAGE;

EID: 0035334798     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.918909     Document Type: Article

References (10)

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