-
2
-
-
0029179466
-
Increasing superscalar performance through multistreaming
-
Jun
-
W. Yamamoto, and M. Nemirovsky,"Increasing superscalar performance through multistreaming", In Proceedings of PACT, Jun, 1995.
-
(1995)
Proceedings of PACT
-
-
Yamamoto, W.1
Nemirovsky, M.2
-
3
-
-
0029666641
-
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
-
D. Tullsen, S. Eggers, J. Emer, H. Levy, J. Lo, and R. Stamm,"Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor", In proc. of 23nd Annual International Symposium on Computer Architecture, 1996.
-
(1996)
proc. of 23nd Annual International Symposium on Computer Architecture
-
-
Tullsen, D.1
Eggers, S.2
Emer, J.3
Levy, H.4
Lo, J.5
Stamm, R.6
-
5
-
-
0003926727
-
Complexity-Effective Superscalar Processors
-
Ph.D. thesis, Univ. of Winsconsin-Madison
-
S. Palacharla, "Complexity-Effective Superscalar Processors", Ph.D. thesis, Univ. of Winsconsin-Madison, 1998.
-
(1998)
-
-
Palacharla, S.1
-
7
-
-
0031594003
-
Dynamic IPC/clock rate optimization
-
June
-
D. Albonesi, "Dynamic IPC/clock rate optimization", Proceedings of ISCA-25, June 1998.
-
(1998)
Proceedings of ISCA-25
-
-
Albonesi, D.1
-
8
-
-
0032639289
-
The Alpha 21264 Microprocessor
-
March/April
-
R. Kessler, "The Alpha 21264 Microprocessor", IEEE Micro, 19(2):24-36, March/April 1999.
-
(1999)
IEEE Micro
, vol.19
, Issue.2
, pp. 24-36
-
-
Kessler, R.1
-
9
-
-
0032592098
-
Deep-Submicron Microprocessor Design Issues
-
July/August
-
M.J. Flynn, P. Hung, and K. Rudd,"Deep-Submicron Microprocessor Design Issues", IEEE Micro, 19(4): 11-22, July/August 1999.
-
(1999)
IEEE Micro
, vol.19
, Issue.4
, pp. 11-22
-
-
Flynn, M.J.1
Hung, P.2
Rudd, K.3
-
10
-
-
0003720587
-
Low-Power High-Performance Superscalar Architectures
-
PhD Thesis, Dept. of Computer Science and Engineering, University of Notre Dame, Jan
-
V.V. Zyuban, "Low-Power High-Performance Superscalar Architectures", PhD Thesis, Dept. of Computer Science and Engineering, University of Notre Dame, Jan. 2000.
-
(2000)
-
-
Zyuban, V.V.1
-
13
-
-
0034462014
-
Instruction Distribution Heuristics for Quad-Cluster, Dynamically-Scheduled, Superscalar Processors
-
December
-
A. Baniasadi, and A. Moshovos, "Instruction Distribution Heuristics for Quad-Cluster, Dynamically-Scheduled, Superscalar Processors", In Proc. of the 33rd. Ann. Intl. Symp. On Microarchitecture, pp. 337-347, December 2000.
-
(2000)
Proc. of the 33rd. Ann. Intl. Symp. On Microarchitecture
, pp. 337-347
-
-
Baniasadi, A.1
Moshovos, A.2
-
14
-
-
0003278283
-
The Microarchitecture of the Pentium® 4 Processor
-
February
-
G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P. Roussel, "The Microarchitecture of the Pentium® 4 Processor", Intel Technology Journal, February 2001.
-
(2001)
Intel Technology Journal
-
-
Hinton, G.1
Sager, D.2
Upton, M.3
Boggs, D.4
Carmean, D.5
Kyker, A.6
Roussel, P.7
-
15
-
-
0034839435
-
Power and Energy Reduction Via Pipeline Balancing
-
July
-
R. Iris Bahar, and S. Manne, "Power and Energy Reduction Via Pipeline Balancing", In Proceedings of ISCA-28, July 2001.
-
(2001)
Proceedings of ISCA-28
-
-
Iris Bahar, R.1
Manne, S.2
-
16
-
-
84962184017
-
An Empirical Study of the Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors
-
A. Aggarwal, and M. Franklin,"An Empirical Study of the Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors", In Proceedings of ISPASS, 2001.
-
(2001)
Proceedings of ISPASS
-
-
Aggarwal, A.1
Franklin, M.2
-
17
-
-
84962144701
-
Balancing throughput and fairness in SMT processors
-
K. Luo, J. Gummaraju, and M. Franklin, "Balancing throughput and fairness in SMT processors", In Proc. of the International Symposium on Performance Analysis of Systems and Software, pages 164-171, 2001.
-
(2001)
In Proc. of the International Symposium on Performance Analysis of Systems and Software
, pp. 164-171
-
-
Luo, K.1
Gummaraju, J.2
Franklin, M.3
-
18
-
-
84962199072
-
How to Compare the Performance of Two SMT Microarchitectures
-
Y. Sazeides, and T. Juan, "How to Compare the Performance of Two SMT Microarchitectures", In Proc. of ISPASS 2001.
-
(2001)
Proc. of ISPASS
-
-
Sazeides, Y.1
Juan, T.2
-
19
-
-
0035696665
-
Handling long-latency loads in a simultaneous multithreading processor
-
Austin, Texas, USA, December 1-5
-
Dean M. Tullsen, and Jeffery A. Brown, "Handling long-latency loads in a simultaneous multithreading processor", In Proc. of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001.
-
(2001)
Proc. of the 34th Annual International Symposium on Microarchitecture
-
-
Tullsen, D.M.1
Brown, J.A.2
-
21
-
-
0038346226
-
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors
-
June
-
R. Balasubramonian, S. Dwarkadas, and D. Albonesi, "Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors", In Proceedings of the ISCA-30, June 2003.
-
(2003)
Proceedings of the ISCA-30
-
-
Balasubramonian, R.1
Dwarkadas, S.2
Albonesi, D.3
-
22
-
-
0038684769
-
Improving dynamic cluster assignment for clustered trace cache processors
-
June
-
R. Bhargava, and L. John Friendly, "Improving dynamic cluster assignment for clustered trace cache processors", In Proceedings of the ISCA-30, June 2003.
-
(2003)
Proceedings of the ISCA-30
-
-
Bhargava, R.1
John Friendly, L.2
-
23
-
-
1142280992
-
Partitioned First-Level Cache Design for Clustered Microarchitectures
-
P. Racunas, and Yale N. Patt, "Partitioned First-Level Cache Design for Clustered Microarchitectures", In proceedings of ICS, 2003.
-
(2003)
proceedings of ICS
-
-
Racunas, P.1
Patt, Y.N.2
-
25
-
-
4143075988
-
Improving Memory Latency Aware Fetch Policies for SMT Processors
-
Oct
-
F. Cazorla, E. Fernandez, A. Ramirez, and M. Valero, "Improving Memory Latency Aware Fetch Policies for SMT Processors", Proc. Fifth Int'l Symp. High Performance Computing (ISHPC), Oct. 2003.
-
(2003)
Proc. Fifth Int'l Symp. High Performance Computing (ISHPC)
-
-
Cazorla, F.1
Fernandez, E.2
Ramirez, A.3
Valero, M.4
-
26
-
-
0038633602
-
Hyperthreading technology in the netburst microarchitecture
-
pages, March-April
-
D. Koufati, and D.T. Marr, "Hyperthreading technology in the netburst microarchitecture", Appears in IEEE Micro, Vol. 23 Issue 2 page(s) 56-65; March-April 2003.
-
(2003)
Appears in IEEE Micro
, vol.23
, Issue.2
, pp. 56-65
-
-
Koufati, D.1
Marr, D.T.2
-
28
-
-
8344263016
-
Back-end Assignment Schemes for Clustered Multithreaded Processors
-
F. Latorre, J. González, and A. González, "Back-end Assignment Schemes for Clustered Multithreaded Processors", In Proceedings of ICS, 2004.
-
(2004)
Proceedings of ICS
-
-
Latorre, F.1
González, J.2
González, A.3
-
29
-
-
12444282715
-
Clustered Multithreaded Architectures -- Pursuing Both IPC and Cycle Time
-
April
-
J. D. Collins, and D. M. Tullsen, "Clustered Multithreaded Architectures -- Pursuing Both IPC and Cycle Time", In proc. of 18th IPDPS, April, 2004.
-
(2004)
proc. of 18th IPDPS
-
-
Collins, J.D.1
Tullsen, D.M.2
-
30
-
-
21644443801
-
Dynamically Controlled Resource Allocation in SMT Processors
-
IEEE Computer Society, December
-
F. J. Cazorla, A. Ramirez, M. Valero, and E. Fernandez, "Dynamically Controlled Resource Allocation in SMT Processors", In Proceedings of the 37th International Symposium on Microarchitecture, pages 171-182. IEEE Computer Society, December 2004.
-
(2004)
Proceedings of the 37th International Symposium on Microarchitecture
, pp. 171-182
-
-
Cazorla, F.J.1
Ramirez, A.2
Valero, M.3
Fernandez, E.4
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