BonnTools: Mathematical innovation for layout and timing closure of systems on a chip

Proceedings of the IEEE

Volumn 95, Issue 3, 2007, Pages 555-572

  Korte, Bernhard ^a   Rautenbach, Dieter ^a   Vygen, Jens ^a  

^a UNIVERSITY OF BONN   (Germany)

Author keywords

Clock tree synthesis; Layout; Physical design; Placement; Routing; Timing optimization

Indexed keywords

CLOCK DISTRIBUTION NETWORKS; ELECTRIC CLOCKS; FORESTRY; SYSTEM-ON-CHIP; TIMING CIRCUITS;

CLOCK TREE SYNTHESIS; LAYOUT; PHYSICAL DESIGN; PLACEMENT; ROUTING; TIMING OPTIMIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 50249146960     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2006.889373     Document Type: Article

References (48)

1. C. Albrecht, "Global routing by new approximation algorithms for multicommodity flow," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 5, pp. 622-632, May 2001.
2. C. Albrecht, B. Korte, J. Schietke, and J. Vygen, "Cycle time and slack optimization for VLSI-chips, in Proc. IEEE Int. Conf. Computer-Aided Design, 1999, pp. 232-238.
3. C. Albrecht, B. Korte, J. Schietke, and J. Vygen, "Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip," Discrete Appl. Math., vol. 123, pp. 103-127, 2002.
4. C. Bartoschek, S. Held, D. Rautenbach, and J. Vygen, "Efficient generation of short and fast repeater tree topologies," in Proc. Int. Symp. Physical Design, 2006, pp. 120-127.
5. U. Brenner, "A faster polynomial algorithm for the unbalanced Hitchcock transportation problem," Research Institute for Discrete Mathematics, Univ. Bonn, Bonn, Germany, Rep. 05 954, 2005.
6. U. Brenner, A. Pauli, and J. Vygen, "Almost optimal placement legalization by minimum cost flow and dynamic programming," in Proc. Int. Symp. Physical Design, 2004, pp. 2-9.
7. U. Brenner and A. Rohe, "An effective congestion driven placement framework," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 4, pp. 387-394, Apr. 2003.
8. U. Brenner and M. Struzyna, "Faster and better global placement by a new transportation problem," in Proc. 42nd IEEE/ACM Design Automation Conf., 2005, pp. 591-596.
9. U. Brenner and J. Vygen, "Faster optimal single-row placement with fixed ordering," in Proc. IEEE Design, Automation and Test in Europe 2000, pp. 117-121.
10. U. Brenner and J. Vygen, "Worst-case ratios of networks in the rectilinear plane," Networks, vol. 38, pp. 126-139, 2001.
11. U. Brenner and J. Vygen, "Legalizing a placement with minimum total movement," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 12, pp. 1597-1613, Dec. 2004.
12. R. C. Carden, IV, J. Li, and C.-K. Cheng, "A global router with a theoretical bound on the optimal solution," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 15, no. 2, pp. 208-216, Feb. 1996.
13. C.-P. Chen, C. C. N. Chu, and D. F. Wong, "Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 7, pp. 1014-1025, Jul. 1999.
14. U. Fassnacht and J. Schietke, "Timing analysis and optimization of a high-performance CMOS processor chipset," in Proc. IEEE Design, Automation and Test in Europe 1998, pp. 325-331.
15. M. L. Fredman and R. E. Tarjan, "Fibonacci heaps and their uses in improved network optimization problems," J. ACM, vol. 34, pp. 596-615, 1987.
16. N. Garg and J. Könemann, "Faster and simpler algorithms for multicommodity flow and other fractional packing problems," in Proc. 39th Annu. IEEE Symp. Foundations of Computer Science, 1998, pp. 300-309.
17. S. Held, "Algorithms for potential balancing problems and applications in VLSI design," (in German), Diploma thesis, Univ. Bonn, Bonn, Germany, 2001.
18. S. Held, B. Korte, J. Maßberg, M. Ringe, and J. Vygen, "Clock scheduling and clocktree construction for high performance ASICs, in Proc. IEEE Int. Conf. Computer-Aided Design, 2003, pp. 232-239.
19. A. Hetzel, "A sequential detailed router for huge grid graphs," in Proc. IEEE Design, Automation and Test in Europe 1998, pp. 332-338.
20. A. B. Kahng, P. Tucker, and A. Zelikovsky, "Optimization of linear placements for wirelength minimization with free sites," in Proc. Asia and South Pacific Design Automation Conf., 1999, pp. 241-244.
21. R. M. Karp, "A characterization of the minimum mean cycle in a digraph," Discrete Math., vol. 23, pp. 309-311, 1978.
22. J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich, "GORDIAN: VLSI placement by quadratic programming and slicing optimization," EEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 10, no. 3, pp. 356-365, Mar. 1991.
23. J. Koehl, U. Baur, T. Ludwig, B. Kick, and T. Pflueger, "A flat, timing-driven design system for a high-performance CMOS processor chipset," in Proc. IEEE Design, Automation and Test in Europe 1998, pp. 312-320.
24. J. Koehl, D. E. Lackey, and G. W. Doerre, "IBM's 50 million gate ASICs," in Proc. IEEE Asia and South Pacific Design Automation Conf. 2003, pp. 628-634.
25. B. Korte, L. Lovász, H. J. Prömel, and A. Schrijver, Eds. Paths, Flows, and VLSI-Layout. Berlin, Germany: Springer, 1990.
26. B. Korte and J. Vygen, Combinatorial Optimization: Theory and Algorithms, 3rd. ed. Berlin, Germany: Springer, 2006.
27. J. Maßberg and J. Vygen, "Approximation algorithms for network design and facility location with service capacities," Approximation, Randomization and Combinatorial Optimization: Proc. 8th International Workshop on Approximation Algorithms for Combinatorial Optimization Problems (APPROX 2005), C. Chekuri, K. Jansen, J. D. P. Rolim, and L. Trevisan, Eds., 2005, pp. 158-169.
28. M. Minoux, Mathematical Programming: Theory and Algorithms. Chichester, U.K.: Wiley, 1986.
29. D. Müller, "Determining routing capacities in global routing of VLSI chips," (in German), Diploma thesis, Univ. Bonn, Bonn Germany, 2002.
30. D. Müller, "Optimizing yield in global routing," in Proc. IEEE Int. Conf. Computer-Aided Design, 2006.
31. S. Peyer, D. Rautenbach, and J. Vygen, "A generalization of Dijkstra's shortest path algorithm with applications to VLSI routing," Research Institute for Discrete Mathematics, Univ. Bonn, Bonn, Germany, Rep. 06 964, 2006.
32. S. Philips and M. Dessouky, "Solving the project time/cost tradeoff problem using the minimal cut concept," Manage. Sci., vol. 24, pp. 393-400, 1977.
33. P. Raghavan and C. D. Thompson, "Randomized rounding: A technique for provably good algorithms and algorithmic proofs," Combinatorica, vol. 7, pp. 365-374, 1987.
34. P. Raghavan and C. D. Thompson, "Multiterminal global routing: A deterministic approximation," Algorithmica, vol. 6, pp. 73-82, 1991.
35. D. Rautenbach, C. Szegedy, and J. Werber, "Delay optimization of linear depth Boolean circuits with prescribed input arrival times," J. Discrete Algorithms, vol. 4, pp. 526-537, 2006.
36. D. Rautenbach, C. Szegedy, and J. Werber, "Fast circuits for functions whose inputs have specified arrival times," Research Institute for Discrete Mathematics, Univ. Bonn, Bonn, Germany, Rep. 03 933, 2003.
37. D. Rautenbach, C. Szegedy, and J. Werber, "Asymptotically optimal Boolean circuits for functions of the form gn-1(gn-2(⋯ g3(g2(g1(x1, x2), x3), x4) ⋯ , xn-1), xn)," Research Institute for Discrete Mathematics, Univ. Bonn, Bonn, Germany, Rep. 03 931, 2003.
38. D. Rautenbach and C. Szegedy, "A class of problems for which cyclic relaxation converges linearly," Computational Optimization and Applications, to be published.
39. D. Rautenbach and C. Szegedy, "A subgradient method using alternating projections," Research Institute for Discrete Mathematics, Univ. Bonn, Bonn, Germany, Rep. 04 940, 2004.
40. H. Schneider and M. H. Schneider, "Max-balancing weighted directed graphs and matrix scaling," Math. Oper. Res., vol. 16, pp. 208-222, 1991.
41. F. Shahrokhi and D. W. Matula, "The maximum concurrent flow problem," J. ACM, vol. 37, pp. 318-334, 1990.
42. J. Vygen, "Algorithms for large-scale flat placement," in Proc. 34th IEEE/ACM Design Automation Conf., 1997, pp. 746-751.
43. J. Vygen, "Algorithms for detailed placement of standard cells," in Proc. IEEE Design, Automation and Test in Europe 1998, pp. 321-324.
44. J. Vygen, "Near-optimum global routing with coupling, delay bounds, and power consumption," Integer Programming and Combinatorial Optimization: Proc. 10th Int. IPCO Conf., G. Nemhauser and D. Bienstock, Eds., 2004, pp. 308-324.
45. J. Vygen, "Geometric quadrisection in linear time, with application to VLSI placement," Discrete Optim., vol. 2, pp. 362-390, 2005.
46. J. Vygen, "Slack in static timing analysis," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 9, pp. 1876-1885, Sep. 2006.
47. J. Vygen, "New theoretical results on quadratic placement," Integr. VLSI J., vol. 40, pp. 305-314, 2007.
48. N. E. Young, R. E. Tarjan, and J. B. Orlin, "Faster parametric shortest path and minimum balance algorithms," Networks, vol. 21, pp. 205-221, 1991.