A flat, timing-driven design system for a high-performance CMOS processor chipset

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 312-320

  Koehl, Juergen ^a   Baur, Ulrich ^a   Ludwig, Thomas ^a   Kick, Bernhard ^a   Pflueger, Thomas ^a  

^a IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CUSTOM DESIGN; CYCLE TIME; DESIGN SYSTEMS; HIGH-PERFORMANCE CMOS; INTERCONNECT DELAY; OPTIMIZED SOLUTIONS; STANDARD CELL; TIMING-DRIVEN;

DATA FLOW ANALYSIS;

DESIGN;

EID: 27744605313     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655874     Document Type: Conference Paper

References (13)

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