Timing analysis and optimization of a high-performance CMOS processor chipset

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 325-331

  Fassnacht, Uwe ^a   Schietke, Juergen ^b  

^a IBM   (Germany)

^b UNIVERSITY OF BONN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHIPSET; HIGH-PERFORMANCE CMOS; OPTIMIZATION METHODOLOGY; OPTIMIZATION SCHEME; STATIC TIMING ANALYSIS; TIMING ANALYSIS;

OPTIMIZATION;

EID: 50549099802     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655876     Document Type: Conference Paper

References (12)

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