An effective congestion-driven placement framework

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 4, 2003, Pages 387-394

  Brenner, Ulrich ^a   Rohe, André ^a,b  

^a UNIVERSITY OF BONN   (Germany)

^b SUN MICROSYSTEMS   (United States)

Author keywords

Congestion driven placement; Physical design; Routability; Very large scale integration (VLSI)

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; ESTIMATION; OPTIMIZATION; VLSI CIRCUITS;

CONGESTION DRIVEN PLACEMENT; PHYSICAL DESIGN; ROUTABILITY PROBLEMS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037390841     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.809662     Document Type: Article

References (23)

1. C. Albrecht, "Global routing by new approximation algorithms for multicommodity flow," IEEE Trans. Computer-Aided Design, vol. 20, pp. 622-632, May 2001.
2. A. E. Caldwell, A. B. Kahng, and I. L. Markov, "Can recursive bisection alone produce routable placements?," in Proc. 37th Design Automation Conf., 2000, pp. 477-482.
3. C.-L. E. Cheng, "RISA: Accurate and efficient placement routability modeling," in Proc. Int. Conf. Computer-Aided Design, 1994, pp. 690-697.
4. H. Eisenmann and F. Johannes, "Generic global placement and floor-planning," in Proc. Design Automation Conf., 1998, pp. 269-274.
5. W. Hou, H. Yu, X. Hong, Y. Cai, W. Wu, J. Gu, and W. H. Kao, "A new congestion-driven placement algorithm based on cell inflation," in Proc. Conf. Asia South Pacific Design Automation, 2001, pp. 605-608.
6. D. Huang and A. Kahng, "Partitioning-Based Standard-Cell Global Placement with an Exact Objective," in Proc. Int. Symp. Physical Design, Napa Valley, CA, 1997, pp. 18-25.
7. P. Hung and M. J. Flynn, "Stochastic congestion model for VLSI Systems," Stanford Univ., CSL-TR-97-737.
8. J. Lou, S. Krishnamoorthy, and H. S. Sheng, "Estimating routing congestion using probabilistic analysis," in Proc. Int. Symp. Physical Design, 2001, pp. 112-117.
9. S. Mayrhofer and U. Lauther, "Congestion-driven placement using a new multi-partitioning heuristic," in Proc. Int. Conf. Computer-Aided Design, 1990, pp. 332-335.
10. P. N. Parakh, R. B. Brown, and K. A. Sakallah, "Congestion driven quadratic placement," in Proc. Design Automation Conf., 1998, pp. 275-278.
11. S. M. Sait and H. Youssef, VLSI Physical Design Automation, Singapore: World Scientific, 1999.
12. M. Sarrafzadeh and C. K. Wong, An Introduction to VLSI Physical Design. New York: McGraw-Hill, 1996.
13. C. Sechen, VLSI Placement and Global Routing Using Simulated Annealing. Norwell, MA: Kluwer, 1988.
14. N. Sherwani, Algorithms for VLSI Physical Design Automation, 3rd ed. Norwood, MA: Kluwer, 1998.
15. J. Vygen, "Algorithms for large-scale flat placement," in Proc. Design Automation Conf., 1997, pp. 746-751.
16. M. Wang and M. Sarrafzadeh, "On the behavior of congestion minimization during placement," in Proc. Int. Symp. Physical Design, 1999, pp. 145-150.
17. ____, "Modeling and minimization of routing congestion," in Proc. Conf. Asia South Pacific Design Automation, 2000, pp. 185-190.
18. M. Wang, X. Yang, K. Eguro, and M. Sarrafzadeh, "Multi-center congestion estimation and minimization during placement," in Proc. Int. Symp. Physical Design, 2000, pp. 147-152.
19. M. Wang, X. Yang, and M. Sarrafzadeh, "Congestion minimization during placement," IEEE Trans. Computer-Aided Design, vol. 19, pp. 1140-1148, Oct. 2000.
20. ____, "Dragon2000: Standard-cell placement tool for large industry designs," in Proc. Int. Conf. Computer-Aided Design, 2000, pp. 260-263.
21. D. F. Wong, H. W. Leong, and C. L. Liu, Simulated Annealing for VLSI Design. Norwell, MA: Kluwer, 1988.
22. X. Yang, R. Kastner, and M. Sarrafzadeh, "Congestion estimation during top-down placement," in Proc. Int. Symp. Physical Design, 2001, pp. 164-170.
23. ____, "Congestion reduction during placement based on integer programming," in Proc. Int. Conf. Computer-Aided Design, 2001, pp. 573-576.