Automated techniques for synthesis of application-specific network-on-chip architectures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 8, 2008, Pages 1425-1438

  Chatha, Karam S ^a,b   Srinivasan, Krishnan ^c,d   Konjevod, Goran ^b  

^a IEEE

^b AZ 85281   (United States)

^c ARIZONA STATE UNIVERSITY   (United States)

^d Sonics Inc   (Canada)

Author keywords

Application specific integrated circuit (ASIC); Approximation methods; Design automation; Network on chip

Indexed keywords

APPROXIMATION ALGORITHMS; BENCHMARKING; COMPUTER ARCHITECTURE; CONFORMAL MAPPING; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; NETWORK ARCHITECTURE; OPTIMIZATION; ROUTING ALGORITHMS; STAGES; TOPOLOGY;

APPLICATION SPECIFIC NETWORK; AUTOMATED SYNTHESIS; AUTOMATED TECHNIQUES; BENCHMARK APPLICATIONS; NETWORK-ON-CHIP (NOC) ARCHITECTURE; OPTIMIZATION OBJECTIVES; PAPER ADDRESSES; POWER CONSUMPTION (CE); RESOURCE USAGE; ROUTE GENERATION; TOPOLOGY GENERATION; TWO STAGES;

ROUTERS;

EID: 47849093510     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.925775     Document Type: Article

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