Integration challenges and opportunities for nanometer scale dual metal gate CMOSFET

ECS Transactions

Volumn 11, Issue 6, 2007, Pages 315-329

  Song, S C ^a   Hussain, M ^a   Barnett, J ^a   Park, C S ^a   Park, C ^a   Kirsch, P ^a   Lee, B H ^a   Jammy, R ^a  

^a SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC MATERIALS; HIGH-K DIELECTRIC; LOW-K DIELECTRIC; METALS; SILICA; SILICON;

CMOS FIELD-EFFECT TRANSISTORS; DUAL METAL GATE; EQUIVALENT OXIDE THICKNESS; INTEGRATION SCHEME; INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS; NANO-METER SCALE; PHYSICAL THICKNESS; TUNNELING CURRENT;

MOSFET DEVICES;

EID: 45749146578     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2778389     Document Type: Conference Paper

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