Electromagnetic interference (EMI) of system-on-package (SOP)

IEEE Transactions on Advanced Packaging

Volumn 27, Issue 2, 2004, Pages 304-314

  Sudo, Toshio ^a   Sasaki, Hideki ^b   Masuda, Norio ^b   Drewniak, James L ^c  

^a TOSHIBA CORPORATION   (Japan)

^b NEC CORPORATION   (Japan)

^c MISSOURI UNIVERSITY OF SCIENCE AND TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTROMAGNETIC FIELD MEASUREMENT; ELECTROMAGNETIC WAVE EMISSION; ELECTROOPTICAL EFFECTS; INTEGRATED CIRCUIT LAYOUT; LSI CIRCUITS; MAGNETOOPTICAL EFFECTS; MATHEMATICAL MODELS; PRINTED CIRCUIT BOARDS; SIGNAL INTERFERENCE;

DC POWER BUS; INTEGRATED CIRCUIT ELECTROMAGNETIC MODEL; POWER INTEGRITY; SIGNAL INTEGRITY; SYSTEM-ON-PACKAGE;

CHIP SCALE PACKAGES;

EID: 4544226060     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2004.828817     Document Type: Article

References (61)

1. D. Gerke, "Fundamentals of EMC design," in Proc. IEEE Int. EMC Symp., Workshop and Tutorials, Washington, DC, 2000. WS1.
2. S. Criel, F. Bonjean, R. DeSmedt, J. DeMoerloose, L. Martens, F. Olyslager, and D. DeZutter, "Accurate characterization of some radiative EMC phenomena at chip level, using dedicated EMC-testchip," in Proc. IEEE Int. EMC Symp., 1998, pp. 734-738.
3. S. Criel, F. Bonjean, R. DeSmedt, and P. DeLanghe, "Design and characterization of an active, EMC-dedicated test chip," in Proc. IEEE Int. EMC Symp., Seattle, WA, 1999, pp. 905-908.
4. L. van Wershoven, "Characterization of an EMC test-chip," in Proc. IEEE Int. EMC Symp., Washington, DC, 2000, pp. 117-121.
5. PQT. Steinecke, W. John, J. Koehne, and M. Schmidt, "EMC modeling and simulation on chip level," in Proc. IEEE Int. Electromagn. Comp. Symp., Montreal, Canada, 2001, pp. 107-112.
6. J.-L. Levant, M. Ramdani, and R. Perdriau, "Power-supply network modeling," in Conf. Proc. Electromagn. Comp., 2002, pp. 75-78.
7. Electromagn. Comp. Part 3: Integrated Circuits Electrical Modeling (ICEM), 2002. IEC Standard Proposal.
8. O. Wada, Y. Takahata, Y. Toyota, R. Koga, T. Miyashita, and Y. Fukumoto, "Power current model of digital IC with internal impedance for power decoupling simulation," in 4th Europ. Electromagn. Compat. Symp., 2000, pp. 315-320.
9. Y. Fukumoto, T. Matsuishi, T. Kinoshita, O. Wada, Y. Toyota, and R. Koga, "Power current model of LSI and parameter identification for EMI simulation of digital PCBs," in Conf. Proc. IEEE Int. Electromagn. Comp. Symp., 2001, pp. 1185-1190.
10. H. Irio, H. Wabuka, N. Tamaki, N. Masuda, and H. Tohya, "HSPICE simulation of power supply current from LSI on PCB with behavioral model," in 1999 Int. Symp. Electromagn. Comp., Tokyo, Japan, 1999, pp. 224-227.
11. R. Evans and M. Tsuk, "Modeling and measurement of a high-performance computer power distribution system," IEEE Trans. Comp. Packag. Manufact. Technol. B, vol. 17, pp. 467-471, Nov. 1994.
12. J. P. Libous and D. P. O'Connor, "Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA," IEEE Trans. Comp. Packag. Manufact. Technol. B, vol. 20, pp. 266-271, Aug. 1997.
13. N. Na, J. Choi, M. Swaminathan, J. P. Libous, and D. P. O'Connor, "Modeling and simulation of core switching noise for ASICs," IEEE Trans. Adv. Packag., vol. 25, Feb. 2002.
14. M. Ingels and M. Steyaert, "Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's," IEEE J. Solid-State Circuits, vol. 32, pp. 1136-1141, July 1997.
15. T. J. Gabara, W. C. Fischer, J. Harrington, and W. W. Troutman, "Forming damped LRC circuits in simultaneously switched CMOS output buffers," IEEE J. Solid-State Circuits, pp. 407-418, 1997.
16. L. Smith, R. E. Anderson, and T. Roy, "Chip-package resonance in core power supply structure for a high power microprocessor," in InterPack 2001, 2001, p. 15 730.
17. E. Diaz-Alvarez and J. P. Krusius, "Package and chip level EMI/EMC structure, design, modeling and simulation," in Conf. Proc. 49th ECTC, 1999, pp. 873-878.
18. W. Woods, E. Diaz-Alvarez, and J. P. Krusius, "Radiative and coupling in BGA packaging for mixed signal and high-speed digital," in Conf. Proc. 51st ECTC, 2001, pp. 511-517.
19. M. J. Hill, J. He, and P. Parmar, "Variations in package radiation due to changes in on-die and on-package capacitance," in Proc. 53rd ECTC, 2003, pp. 1568-1571.
20. Microelectronics Packaging Handbook, Chapman and Hall, New York, 1997. R. Tummala, E. J. Rymaszewski, A. G. Klopfenstein.
21. R. Singh, Signal Integrity Effects in Custom IC and ASIC Designs. New York: Wiley-Interscience, 2002.
22. J. Kim, H. Kim, W. Ryu, Y.-H. Yun, S.-H. Kim, S.-H. Ham, H.-K. An, and Y.-H. Lee, "Effects of on-chip decoupling capacitors on electromagnetic radiated emission," in Conf. Proc. 48th ECTC, 1998, pp. 610-614.
23. PQJ. Kim, B. Choi, H. Kim, W. Ryu, Y.-H. Yun, S.-H. Ham, S.-H. Kim, Y.-H. Lee, and J. Kim, "Separate role of on-chip and on-PCB decoupling capacitors for reduction of radiated emission on printed circuit board," in Conf. Proc. IEEE Int. EMC Symp., Montreal, Canada, 2001, pp. 531-536.
24. T. Sudo, K. Nakano, J. Kudo, and S. Haga, "Characterization of on-chip capacitance effects for I/O circuits and core circuits," in IEEE 10th Top. Meeting EPEP, 2001, pp. 73-76.
25. T. Sudo, K. Nakano, A. Nakamura, and S. Haga, "A test chip for evaluating switching noise and radiated emission by I/O and core circuits," in Proc. IEEE Int. EMC Symp., Montreal, 2001, pp. 676-680.
26. T. Sudo, J. Kudo, K. Nakano, and S. Haga, "Modeling and characterization of switching noise and signal waveforms using test chips," in Electromagn. Compat. Europe 2002, 2002, pp. 503-506.
27. S. H. Hall, G. W. Hall, and J. A. McCall, High-Speed Digital System Design. New York: Wiley-Interscience, 2000, ch. 3.
28. S. Ohtsu, K. Nahase, and T. Yamagajou, "Analysis of radiation caused by LSI package cross talk and cable by using the time-domain moment method," in Proc. IEEE Int. Electromagn. Compat. Symp., Aug. 2002, pp. 268-272.
29. J. Chen, T. H. Hubing, T. P. Van Dorn, and R. E. DuBroff, "Power bus isolation using power islands in printed circuit boards," IEEE Trans. Electromagn. Compat., vol. 44, pp. 373-380, May 2002.
30. T. H. Hubing, J. L. Drewniak, T. P. Van Doren, and D. M. Hockanson, "Power bus decoupling on multilayer printed circuit boards," IEEE Trans. Electromagn. Compat., vol. 37, pp. 155-166, May 1995.
31. Y. Ko, K. Ito, J. Kudo, and T. Sudo, "Electromagnetic radiation properties of printed circuit board with a slot in the ground plane," in Proc. IEEE Int. Symp. Electromagn. Compat., Tokyo, May 1999, pp. 576-579.
32. L. Jyh-Haw and H. Merkelo, "Signal integrity issues at split ground and power planes," in Proc. 46th ECTC, 1996, pp. 752-755.
33. W. Cui, X. Ye, B. Archambeault, D. White, M. Li, and J. L. Drewniak, "Modeling EMI resulting from a signal via transition through power/ground layers," in Proc. 16th Ann. Rev. Progress in Applied Computational Electromagnetics, Monterey, CA, Mar. 2000, pp. 436-443.
34. W. Cui, M. Li, X. Luo, J. L. Drewniak, T. H. Hubing, T. P. Van Doren, and R. E. DuBroff, "Anticipating EMI from coupling between high-speed digital and I/O lines," in Proc. IEEE Int. Electromagn. Compat. Symp., Seattle, WA, Aug. 1999, pp. 189-194.
35. W. Cui, X. Ye, B. Archambeault, D. White, M. Li, and J. L. Drewniak, "EMI resulting from a signal via transition through DC power bus - Effectiveness of local SMT decoupling," in Asia-Pacific Conf. Proc. Environmental Electromagn., CEEM'2000, 2000, pp. 91-95.
36. T. Harada, H. Sasaki, and T. Kuriyama, "Radiated emission from a multilayer PCB with traces placed between power/ground planes," in Conf. Proc. IEEE Int. Electromagn. Compat. Symp., Aug. 2002, pp. 253-257.
37. L. D. Smith, "Packaging and power distribution design considerations for a SUN microsystems desktop workstation," in IEEE 6th Top. Meeting on EPEP, Oct. 1997, pp. 19-22.
38. G.-T. Lei, R. W. Techentin, and B. K. Gilbert, "High-frequency characterization of power/ground-plane structures," IEEE Trans. Microwave Theory Tech., vol. 47, May 1995.
39. W. Cui, J. Fan, Y. Ren, H. Shi, J. L. Drewniak, and R. E. DuBroff, "DC power-bus noise isolation with power-plane segmentation," IEEE Trans. Electromagn. Compat., vol. 45, pp. 436-443, May 2003.
40. H. Sasaki, T. Harada, and T. Kuriyama, "A new VLSI decoupling circuit for suppressing radiated emissions from multilayer printed circuit boards," in Proc. IEEE Int. Electromagn. Compat. Symp., Aug. 2000, pp. 157-162.
41. M. Xu, T. H. Hubing, J. Chen, T. P. Van Dorn, J. L. Drewniak, and R. E. DuBroff, "Power-bus decoupling with embedded capacitance in printed circuit board design," IEEE Trans. Electromagn. Compat., vol. 45, pp. 22-30, Feb. 2003.
42. C. R. Paul, Introduction to Electromagnetic Compatibility. New York: Wiley-Interscience, 1992.
43. J. Fan, W. Cui, J. L. Drewniak, T. P. Van Doren, and J. L. Knighten, "Estimating the noise mitigation effect of local decoupling in printed circuit boards," IEEE Trans. Adv. Packag., vol. 25, pp. 154-165, May 2002.
44. J. P. Berenger, "Perfectly matched layer for the absorption of electromagnetic waves," J. Computer Phys., vol. 114, pp. 185-200, Oct. 1994.
45. Advances in Computational Electrodynamics: The Finite-Difference Time-Domain Method. Boston, MA, 1998.
46. X. Ye, M. Koledintseva, M. Li, and J. L. Drewniak, "DC power-bus design using FDTD modeling with dispersive media and surface mount technology," IEEE Trans. Electromagn. Compat., vol. 43, pp. 579-587, Nov. 2001.
47. D. M. Hockanson, J. L. Drewniak, T. H. Hubing, and T. P. Van Doren, "FDTD modeling of common-mode radiation from cables," IEEE Trans. Electromagn. Compat., vol. 38, pp. 376-387, Aug. 1996.
48. Y.-S. Tsuei, A. C. Cangellaris, and J. L. Prince, "Rigorous electromagnetic modeling of chip-to-package (first level) interconnections," IEEE Trans. Comp. Hybrids, Manufact. Technol., vol. 16, pp. 876-882, Dec. 1993.
49. M. Abdul-Gaffoor, H. K. Smith, A. A. Kishk, and A. W. Glisson, "Simple and efficient full-wave modeling of electromagnetic coupling in realistic RF multi-layer PCB layouts," IEEE Trans. Microwave Theory Tech., vol. 50, pp. 1445-1457, June 2002.
50. N. Matsui, N. Orthanovic, and H. Wabuka, "FDTD SPICE analysis of EMI and SSO of LSI/IC's using a full chip macro model," in Conf. Proc. IEEE Int. Electromagn. Compat. Symp., Minneapolis, MN, Aug. 2002, pp. 19-23.
51. O. Wada, Z. L. Wang, S. Matsumoto, R. Koga, T. Watanabe, Y. Fukumoto, O. Shibata, E. Takahashi, and H. Osaka, "High-speed simulation of PCB emission and immunity with frequency-domain IC/LSI," in Conf. Proc. IEEE Int. Electromagn. Compat. Symp., Boston, MA, Aug. 2003, pp. 4-9.
52. C. Lochot and J.-L. Levant, "A new standard for EMC of IC," in Conf. Proc. IEEE Int. Electromagn. Compat. Symp., Boston, MA, Aug. 2003, pp. 892-897.
53. N. Masuda, N. Tamaki, T. Kuriyama, J. C. Bu, and M. Yamaguchi, "High frequency magnetic near field measurement on LSI chip using planar multilayer shielded loop coil," in Conf. Proc. IEEE Int. Electromagn. Compat. Symp., Boston, MA, Aug. 2003, pp. 80-85.
54. N. Ando, N. Masuda, N. Tamaki, T. Kuriyama, and M. Yamaguchi, "Miniaturized magnetic field probe and its application to LSI chip measurement," in Tech. Meet. Phys. Sensors, PHS-03-19, Nov. 2003, pp. 25-30. in Japanese.
55. N. Masuda, N. Tamaki, T. Kuriyama, T. Watanabe, T. Shimasaki, and Y. Shiratori, "Development of a system for measuring high-frequency magnetic fields and currents of LSI's and PCBs," NEC Res. Develop., vol. 44, no. 3, pp. 241-245, July 2003.
56. M. Iwanami, S. Hoshino, M. Kishi, and M. Tsuchiya, "Magnetic near-field distribution measurements over fine meander circuit patterns by fiber-optic magneto-optic probe," in Proc. IEEE Int. Electromagn. Compat. Symp., Boston, MA, Aug. 2003, pp. 347-352.
57. Integrated Circuits - Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz - Part 6: Measurement of Conducted Emissions - Magnetic Probe Method, June 2002.
58. B. Deutschmann and R. Jungreithmair, "Visualizing the electromagnetic emission at the surface of ICs," in IEEE Int. Symp. Electromagn. Compat., Turkey, May 2003.
59. S. Kazama, S. Shinohara, and R. Sato, "Estimation of current and voltage distributions by scanning coupling probe," IEICE Trans. Commun., vol. E83-B, pp. 460-466, Mar. 2000.
60. E. Suzuki, T. Miyakawa, H. Ota, K. I. Arai, and R. Sato, "Optical magnetic field sensing with a loop antenna element doubly-loaded with electro-optic crystals," in Conf. Proc. IEEE Int. Electromagn. Compat. Symp., Boston, MA, Aug. 2003, pp. 442-447.
61. H. Hirayama and Y. Kami, "An imaging system for electromagnetic noise source identification," in Conf. Proc. Electromagn. Compat. Europe 2002, 2002, pp. 609-614.