Power bus isolation using power islands in printed circuit boards

IEEE Transactions on Electromagnetic Compatibility

Volumn 44, Issue 2, 2002, Pages 373-380

  Chen, Juan ^a   Hubing, Todd H ^b   Van Doren, Thomas P ^b   DuBroff, Richard E ^b  

^a INTEL CORPORATION   (United States)

^b MISSOURI UNIVERSITY OF SCIENCE AND TECHNOLOGY   (United States)

Author keywords

Board resonance; Coupling; Power bus isolation; Power island

Indexed keywords

ELECTROMAGNETIC WAVE INTERFERENCE; ENERGY GAP; MAGNETIC COUPLINGS; MAGNETIC RESONANCE; MATHEMATICAL MODELS; PRINTED CIRCUIT BOARDS;

BOARD RESONANCE; POWER BUS ISOLATION; POWER ISLANDS;

ELECTROMAGNETIC COMPATIBILITY;

EID: 0036577213     PISSN: 00189375     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEMC.2002.1003403     Document Type: Article

References (8)

1. Pentium III processor power distribution guidelines
2. Layout guideline for the RC7100 motherboard system clock
3. Power bus noise reduction using power islands in printed circuit board designs
4. RF isolation using power islands in DC power bus design
5. DC power bus noise isolation with power islands
6. An experimental procedure for characterizing interconnects to the DC power bus on a multilayer printed circuit board
7. An experimental investigation of 4-layer printed circuit board decoupling
8. Quantifying decoupling capacitor location