Modeling and simulation of core switching noise for ASICs

IEEE Transactions on Advanced Packaging

Volumn 25, Issue 1, 2002, Pages 4-11

  Na, Nju ^b   Choi, Jinwoo ^a,c   Swaminathan, Madhavan ^a,c   Libous, James P ^d   O'Connor, Daniel P ^d  

^a IEEE   (United States)

^b AGILENT TECHNOLOGIES   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^d IBM MICROELECTRONICS   (United States)

Author keywords

ASICs modeling; Plane modeling; Switching noise simulation

Indexed keywords

SWITCHING NOISE SIMULATION;

CAPACITORS; CAVITY RESONATORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRONICS PACKAGING; FREQUENCY DOMAIN ANALYSIS; PRINTED CIRCUIT BOARDS; RESONANCE; SPURIOUS SIGNAL NOISE; SWITCHING; TIME DOMAIN ANALYSIS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0036479019     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2002.1017678     Document Type: Conference Paper

References (6)

1. Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA
2. Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems
3. Modeling and transient simulation of planes in electronic packages
4. Modeling of simultaneous switching noise in high speed systems
5. Modeling and measurement of the alpha 21 364 package