Characterization of on-chip capacitance effects for I/O circuits and core circuits

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2001, Pages 73-76

  Sudo, Toshio ^a   Nakano, Ken ^a   Kudo, Junichi ^a   Haga, Satoru ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTROMAGNETIC WAVE EMISSION; ELECTRONICS PACKAGING; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MICROSTRIP LINES; PRINTED CIRCUIT BOARDS; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

CORE LOGIC CIRCUITS; INPUT OUTPUT CIRCUITS; RADIATED EMISSION; SIMULTANEOUS SWITCHING NOISE;

INTEGRATED CIRCUIT TESTING;

EID: 0035699324     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Package electrical design
2. Simultaneous switching ground noise calculation for packaged CMOS devices
3. Electrical characterization of package environment using switching noise generating vehicle
4. Characterization and reduction of simultaneous switching noise for multilayer package
5. Measurement, modeling and simulation of flip-chip CMOS ASIC simultaneous and switching noise on a multilayer BGA
6. Design and characterization of an active, EMC-dedicated test chip