EMC modeling and simulation on chiplevel

IEEE International Symposium on Electromagnetic Compatibility

Volumn 2, Issue , 2001, Pages 1191-1196

  Steinecke, T ^a   John, W ^b   Koehne, H ^b   Schmidt, M ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b FRAUNHOFER GESELLSCHAFT   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CORRELATION METHODS; GATES (TRANSISTOR); VLSI CIRCUITS;

DIGITAL MODULES;

ELECTROMAGNETIC COMPATIBILITY;

EID: 0035786077     PISSN: 01901494     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. T. Steinecke, Experimental Characterization of Switching Noise and Signal Integrity in Deep Submicron Integrated Circuits, IEEE EMC 2000, Washington D.C., 2000.
2. W. John, T. Steinecke, H. Könne, R. Niebauer, Methodology for EME reduction on chip level, EMC 2000 Europe, Brugge, 2000.
3. T. Steinecke, Design-In for EMC on Large-Scale Integrated Circuits, Paper and presentation on the IEEE EMC 2001, Montreal.
4. E. Sicard et al., A Cooperative Research for Experimental Characterization of Signal Integrity in Deep Submicron Integrated Circuits, 1999 IEEE International Symposium on Electromagnetic Compatibility, Seattle, USA.
5. Voltage Storm, User Guide, Release 3.0, Simplex Solutions Inc., California USA, 1999.
6. Fast Henry User's Guide, Version 3.0, Massachusetts Institute of Technology, USA, 1996.