Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 3, 1997, Pages 407-417

  Gabara, Thaddeus J ^a   Fischer, Wilhelm C ^a   Harrington, John ^b   Troutman, William W ^a  

^a LUCENT TECHNOLOGIES   (United States)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

Buffer circuits; Noise

Indexed keywords

BUFFER CIRCUITS; CIRCUIT OSCILLATIONS; ELECTRIC NETWORK ANALYSIS; ELECTRIC RESISTANCE; ELECTRIC VARIABLES MEASUREMENT; MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE;

PARASITIC CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0031104003     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.557639     Document Type: Article

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