Power current model of LSI and parameter identification for EMI simulation of digital PCBs

IEEE International Symposium on Electromagnetic Compatibility

Volumn 2, Issue , 2001, Pages 1185-1190

  Fukumoto, Yukihiro ^a   Matsuishi, Takuya ^b   Kinoshita, Tomohiro ^b   Wada, Osami ^b   Toyota, Yoshitaka ^b   Koga, Ryuji ^b  

^a PANASONIC CORPORATION   (Japan)

^b OKAYAMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC IMPEDANCE; SIGNAL INTERFERENCE; VLSI CIRCUITS;

POWER CURRENT MODEL;

PRINTED CIRCUIT BOARDS;

EID: 0035785995     PISSN: 01901494     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. T. Hubing, J. Drewniak, T. V. Doren, and D. Hockanson: "Power bus decoupling on multilayer printed circuit boards," IEEE Trans. on EMC, vol. 37, no. 2, pp. 155-166, May 1995.
2. S. Tani, M. Ozaki, M. Naka, and M. Kotani: "A method for reducing radiated emission from multilayer printed circuit boards with decoupling capacitors," IEICE Technical Report, EMCJ99-57, pp. 35-40, Sep. 1999 (in Japanese).
3. Y. Fukumoto, S. Nakamura, O. Wada, and R. Koga: "A design method of decoupling circuits for a digital PCB to reduce high frequency currents in power and ground planes", 1999 Int. Symp. on EMC ('99 EMC Tokyo), Tokyo, 18P103, pp. 9-12, May 1999.
4. O. Wada, Y. Takahata, Y. Toyota, R. Koga, T. Miyashita, and Y. Fukumoto: "Power current model of digital IC with internal impedance for power decoupling simulation," 4th European Symposium on Electromagnetic Compatibility (EMC Europe 2000 Bruges), Belgium, pp. 315-320, Sept. 2000.
5. K. Shimazaki, S. Hirano, H. Tsujikawa, T. Yoneda, E. Takahashi and Y. Fukumoto: "Analysis of EMI noise from an LSI using a gate level simulator," IEICE Technical Report, EMCJ2000-114, pp. 79-84, December 2000 (in Japanese).