Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 20, Issue 3, 1997, Pages 266-271

  Libous, James P ^a   O'Connor, Daniel P ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

Application specific integrated circuits; Ceramic ball grid array; CMOS integrated circuits; Computer simulation; Delta I noise; Electronics packaging; Flip chip devices; Mathematical models; Signal noise measurement; Simultaneous switching noise

Indexed keywords

CERAMIC MATERIALS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRONICS PACKAGING; FLIP CHIP DEVICES; INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR DEVICE MODELS; SIGNAL NOISE MEASUREMENT; SPURIOUS SIGNAL NOISE; SWITCHING CIRCUITS; TIME DOMAIN ANALYSIS;

CERAMIC BALL GRID ARRAY PACKAGES; SIMULTANEOUS SWITCHING NOISE;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0031197351     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.618226     Document Type: Article

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