메뉴 건너뛰기




Volumn , Issue , 2007, Pages 58-67

Designing analog and RF circuits for ultra-low supply voltages

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL DESIGN; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POTENTIAL; ELECTRONICS INDUSTRY; FREQUENCY CONVERTER CIRCUITS; INTEGRATED CIRCUITS; MICROELECTRONICS; MOS DEVICES; NETWORKS (CIRCUITS); PAPER; THRESHOLD VOLTAGE;

EID: 44849131374     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2007.4430249     Document Type: Conference Paper
Times cited : (14)

References (49)
  • 1
    • 0022121172 scopus 로고
    • Performance Limitations in Switched-Capacitor Filters
    • Sept
    • R. Castello and P.R. Gray, "Performance Limitations in Switched-Capacitor Filters," IEEE Transactions on Circuits and Systems, vol. 32, no. 9, pp. 865-876, Sept. 1985.
    • (1985) IEEE Transactions on Circuits and Systems , vol.32 , Issue.9 , pp. 865-876
    • Castello, R.1    Gray, P.R.2
  • 2
    • 0025660615 scopus 로고
    • Future of analog in the VLSI environment
    • May
    • E. Vittoz, "Future of analog in the VLSI environment," in Proc. ISCAS, May 1990, pp. 1372-1375.
    • (1990) Proc. ISCAS , pp. 1372-1375
    • Vittoz, E.1
  • 5
    • 0003140671 scopus 로고    scopus 로고
    • Analog design in deep sub-micron CMOS, in Proc
    • Sep
    • K. Bult, "Analog design in deep sub-micron CMOS," in Proc. ESSCIRC, Sep. 2000, pp. 11-17.
    • (2000) ESSCIRC , pp. 11-17
    • Bult, K.1
  • 7
    • 17644425346 scopus 로고    scopus 로고
    • Q. Huang, Low voltage and low power aspects of data converter design, in Proceedings European Solid-State Circuits Conference (ESSCIRC), September 2004, pp. 29-35.
    • Q. Huang, "Low voltage and low power aspects of data converter design," in Proceedings European Solid-State Circuits Conference (ESSCIRC), September 2004, pp. 29-35.
  • 9
    • 20444492464 scopus 로고    scopus 로고
    • Device mismatch and Tradeoffs in the Design of Analog Circuits
    • June
    • P. Kinget, "Device mismatch and Tradeoffs in the Design of Analog Circuits", IEEE Journal of Solid-State Circuits, vol. 40, no 6, June 2005, pp. 1212-1224.
    • (2005) IEEE Journal of Solid-State Circuits , vol.40 , Issue.6 , pp. 1212-1224
    • Kinget, P.1
  • 11
    • 33845648437 scopus 로고    scopus 로고
    • Low-Power 2.4-GHz Transceiver With Passive RX Front-End and 400-mV Supply
    • Dec
    • B. Cook, et al., "Low-Power 2.4-GHz Transceiver With Passive RX Front-End and 400-mV Supply", IEEE Journal of Solid-State Circuits, Vol. 41, no 12, pp. 2757-2766, Dec. 2006.
    • (2006) IEEE Journal of Solid-State Circuits , vol.41 , Issue.12 , pp. 2757-2766
    • Cook, B.1
  • 13
    • 25144514874 scopus 로고    scopus 로고
    • Modeling and sizing for minimum energy operation in subthreshold circuits
    • Sept
    • B. Calhoun, A. Wang, and A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits," IEEE Journal of Solid-State Circuits, Vol. 40, no. 9, pp. 1778 - 1786, Sept. 2005.
    • (2005) IEEE Journal of Solid-State Circuits , vol.40 , Issue.9 , pp. 1778-1786
    • Calhoun, B.1    Wang, A.2    Chandrakasan, A.3
  • 14
    • 33748554808 scopus 로고    scopus 로고
    • Ultralow-voltage minimum-energy CMOS
    • July/Sept
    • S. Hanson et al., "Ultralow-voltage minimum-energy CMOS," IBM Journal of Research and Development, vol. 50, no. 4/5, pp. 469-489, July/Sept. 2006.
    • (2006) IBM Journal of Research and Development , vol.50 , Issue.4-5 , pp. 469-489
    • Hanson, S.1
  • 17
    • 0033892267 scopus 로고    scopus 로고
    • Low-voltage analog circuit design based on biased inverting opamp configuration
    • Mar
    • S. Karthikeyan, S. Mortezapour, A. Tammineedi, and E. Lee, "Low-voltage analog circuit design based on biased inverting opamp configuration," IEEE Trans. Circuits Syst. II, vol. 47, no. 3, pp. 176-184, Mar. 2000.
    • (2000) IEEE Trans. Circuits Syst. II , vol.47 , Issue.3 , pp. 176-184
    • Karthikeyan, S.1    Mortezapour, S.2    Tammineedi, A.3    Lee, E.4
  • 18
    • 0032664038 scopus 로고    scopus 로고
    • A 1.5-V, 10 bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
    • May
    • A. Abo and P. Gray, "A 1.5-V, 10 bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , Issue.5 , pp. 599-606
    • Abo, A.1    Gray, P.2
  • 19
    • 0001549309 scopus 로고
    • Body driven differential amplifier for application in continuous-time active-C filter
    • A. Guzinski, M. Bialko, and J. Matheau, "Body driven differential amplifier for application in continuous-time active-C filter," in Proc. ECCD, 1987, pp. 315-319.
    • (1987) Proc. ECCD , pp. 315-319
    • Guzinski, A.1    Bialko, M.2    Matheau, J.3
  • 20
    • 0028044343 scopus 로고    scopus 로고
    • T. Kobayashi and T. Sakurai, Self-adjusting threshold-voltage scheme (SATS) for low- voltage high-speed operation, in Proc. IEEE Custom Integrated Circuits Conference, May 1994, pp. 271-274.
    • T. Kobayashi and T. Sakurai, "Self-adjusting threshold-voltage scheme (SATS) for low- voltage high-speed operation," in Proc. IEEE Custom Integrated Circuits Conference, May 1994, pp. 271-274.
  • 21
    • 0028755812 scopus 로고
    • Automatic adjustment of threshold and supply voltages for minimum power consumption in CMOS digital circuits
    • V. R. Kaenel, et al., "Automatic adjustment of threshold and supply voltages for minimum power consumption in CMOS digital circuits," in Proc. (IEEE) Symposium on Low Power Electronics, 1994, pp. 78-79.
    • (1994) Proc. (IEEE) Symposium on Low Power Electronics , pp. 78-79
    • Kaenel, V.R.1
  • 22
    • 2442647559 scopus 로고    scopus 로고
    • Ultra-low voltage circuits and processor in 180 nm to 90 nm technologies with a swapped-body biasing technique
    • Papers, 2004, pp
    • S. Narendra, et al., "Ultra-low voltage circuits and processor in 180 nm to 90 nm technologies with a swapped-body biasing technique," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2004, pp. 156-157.
    • IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech , pp. 156-157
    • Narendra, S.1
  • 23
    • 29044442913 scopus 로고    scopus 로고
    • 0.5 V Analog Circuit Techniques and Their Application in OTA and Filter Design
    • December
    • S. Chatterjee, Y. Tsividis and P. Kinget, "0.5 V Analog Circuit Techniques and Their Application in OTA and Filter Design," IEEE Journal of Solid-State Circuits, vol. 40, no 12, pp. 2373 - 2387, December 2005.
    • (2005) IEEE Journal of Solid-State Circuits , vol.40 , Issue.12 , pp. 2373-2387
    • Chatterjee, S.1    Tsividis, Y.2    Kinget, P.3
  • 24
    • 0028514303 scopus 로고
    • Low-voltage balanced transconductor with high input common-mode rejection
    • Sep
    • A. Baschirotto, F. Rezzi, and R. Castello, "Low-voltage balanced transconductor with high input common-mode rejection," Electron. Lett., vol. 30, no. 20, pp. 1669-1671, Sep. 1994.
    • (1994) Electron. Lett , vol.30 , Issue.20 , pp. 1669-1671
    • Baschirotto, A.1    Rezzi, F.2    Castello, R.3
  • 25
    • 0028483735 scopus 로고
    • Switched-opamp: An approach to realize full CMOS switched-capacitor circuits at very low power-supply voltages
    • Aug
    • J. Crois and M. Steyaert, "Switched-opamp: An approach to realize full CMOS switched-capacitor circuits at very low power-supply voltages," IEEE J. Solid-State Circuits, vol. 29, no. 8, pp. 936-942, Aug. 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , Issue.8 , pp. 936-942
    • Crois, J.1    Steyaert, M.2
  • 26
    • 0036914179 scopus 로고    scopus 로고
    • A 0.7-V MOSFET-only switched-opamp sigma-delta modulator in standard digital CMOS technology
    • Dec
    • J. Sauerbrey, T. Tille, D. Schmitt-Landsiedel, and R. Thewes, "A 0.7-V MOSFET-only switched-opamp sigma-delta modulator in standard digital CMOS technology," IEEE Journal of Solid-State Circuits, Vol. 37, no. 12, pp. 1662 - 1669, Dec. 2002.
    • (2002) IEEE Journal of Solid-State Circuits , vol.37 , Issue.12 , pp. 1662-1669
    • Sauerbrey, J.1    Tille, T.2    Schmitt-Landsiedel, D.3    Thewes, R.4
  • 29
    • 0024915511 scopus 로고
    • An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wideband S/H
    • Dec
    • M. Ishikawa and T. Tsukahara, "An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wideband S/H," IEEE Journal of Solid-State Circuits, vol. 24, no. 12, pp. 1485-1491, Dec. 1989.
    • (1989) IEEE Journal of Solid-State Circuits , vol.24 , Issue.12 , pp. 1485-1491
    • Ishikawa, M.1    Tsukahara, T.2
  • 31
    • 33947697782 scopus 로고    scopus 로고
    • A 0.5-V 1-Msps Track-and-Hold Circuit with 60-dB SNDR
    • April
    • S. Chatterjee, and P. Kinget, "A 0.5-V 1-Msps Track-and-Hold Circuit with 60-dB SNDR," IEEE Journal of Solid-State Circuits, vol. 43, no 4, pp. 722-729, April 2007.
    • (2007) IEEE Journal of Solid-State Circuits , vol.43 , Issue.4 , pp. 722-729
    • Chatterjee, S.1    Kinget, P.2
  • 32
    • 33847741683 scopus 로고    scopus 로고
    • A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator with a Return-to-Open DAC
    • March
    • K.P. Pun, S. Chatterjee, and P. Kinget, "A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator with a Return-to-Open DAC," IEEE Journal of Solid-State Circuits, Vol. 43, no 3, pp. 496-507, March 2007.
    • (2007) IEEE Journal of Solid-State Circuits , vol.43 , Issue.3 , pp. 496-507
    • Pun, K.P.1    Chatterjee, S.2    Kinget, P.3
  • 35
    • 0034476162 scopus 로고    scopus 로고
    • 2-GHz RF Front-end Circuits in CMOS/SIMOX Operating at an Extremely Low Voltage of 0.5V
    • Dec
    • M. Harada, T. Tsukahara, J. Kodate, A. Yamagishi, and J. Yamada, "2-GHz RF Front-end Circuits in CMOS/SIMOX Operating at an Extremely Low Voltage of 0.5V," IEEE Journal of Solid-State Circuits, vol. 35, no. 12, pp. 2000-2004, Dec. 2000.
    • (2000) IEEE Journal of Solid-State Circuits , vol.35 , Issue.12 , pp. 2000-2004
    • Harada, M.1    Tsukahara, T.2    Kodate, J.3    Yamagishi, A.4    Yamada, J.5
  • 38
    • 34548858160 scopus 로고    scopus 로고
    • A. Rylyakov, J. Tierno, G. English, D. Friedman, M. Meghelli, A Wide Power-Supply Range (0.5-to-1.3V) Wide Tuning-Range (500MHz-to-8GHz) All-Static CMOS ADPLL in 65nm SOI, in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC), February 2007.
    • A. Rylyakov, J. Tierno, G. English, D. Friedman, M. Meghelli, "A Wide Power-Supply Range (0.5-to-1.3V) Wide Tuning-Range (500MHz-to-8GHz) All-Static CMOS ADPLL in 65nm SOI," in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC), February 2007.
  • 39
    • 34547286248 scopus 로고    scopus 로고
    • S.A. Yu and P. Kinget, A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC), February 2007.
    • S.A. Yu and P. Kinget, "A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS" in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC), February 2007.
  • 40
    • 0035392122 scopus 로고    scopus 로고
    • Optimum Voltage Swing on On-Chip and Off-Chip Interconnect
    • July
    • C. Svensson, "Optimum Voltage Swing on On-Chip and Off-Chip Interconnect," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1108-1112, July 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.7 , pp. 1108-1112
    • Svensson, C.1
  • 41
    • 33947158623 scopus 로고    scopus 로고
    • Impact of Scaling on Analog Performance and Associated Modeling Needs
    • Sept
    • B. Murmann, P. Nikaeen, D.J. Connelly, and R.W. Dutton, "Impact of Scaling on Analog Performance and Associated Modeling Needs," IEEE Transactions on Electron Devices, Vol. 53, no. 9, pp. 2160-2167, Sept. 2006.
    • (2006) IEEE Transactions on Electron Devices , vol.53 , Issue.9 , pp. 2160-2167
    • Murmann, B.1    Nikaeen, P.2    Connelly, D.J.3    Dutton, R.W.4
  • 42
    • 33947243464 scopus 로고    scopus 로고
    • Planar Bulk MOSFETS Versus FinFETs: An Analog/RF Perspective
    • Dec
    • V. Subramanian et al., "Planar Bulk MOSFETS Versus FinFETs: An Analog/RF Perspective," IEEE Transactions on Electron Devices, Vol. 53, no. 12, pp. 3071-3079, Dec. 2006.
    • (2006) IEEE Transactions on Electron Devices , vol.53 , Issue.12 , pp. 3071-3079
    • Subramanian, V.1
  • 44
    • 33947421763 scopus 로고    scopus 로고
    • Physical insights regarding design and performance of independent-gate FinFETs,
    • Oct
    • W. Zhang et al., "Physical insights regarding design and performance of independent-gate FinFETs,", IEEE Transactions on Electron Devices,Vol. 52, no. 10, pp. 2198-2206, Oct. 2005.
    • (2005) IEEE Transactions on Electron Devices , vol.52 , Issue.10 , pp. 2198-2206
    • Zhang, W.1
  • 45
    • 33646023723 scopus 로고    scopus 로고
    • Analog/RF Performance of Multiple Gate SOI Devices: Wideband Simulations and Characterization
    • May
    • J.P. Raskin et al., "Analog/RF Performance of Multiple Gate SOI Devices: Wideband Simulations and Characterization," IEEE Transactions on Electron Devices,Vol. 53, no. 5, pp. 1088-1095, May 2006.
    • (2006) IEEE Transactions on Electron Devices , vol.53 , Issue.5 , pp. 1088-1095
    • Raskin, J.P.1
  • 46
    • 33748535403 scopus 로고    scopus 로고
    • High-performance CMOS variability in the 65-nm regime and beyond
    • July/Sept
    • K. Bernstein et al., "High-performance CMOS variability in the 65-nm regime and beyond," IBM Journal of Research and Development, vol. 50, no. 4/5, pp. 433-449, July/Sept. 2006.
    • (2006) IBM Journal of Research and Development , vol.50 , Issue.4-5 , pp. 433-449
    • Bernstein, K.1
  • 47
    • 22544440903 scopus 로고    scopus 로고
    • Efficiency of body biasing in 90 nm CMOS for low power digital circuits
    • Jul
    • K. von Arnim, et al., "Efficiency of body biasing in 90 nm CMOS for low power digital circuits," IEEE Journal of Solid-State Circuits, vol. 40, no. 7, pp. 1549-1556, Jul. 2005.
    • (2005) IEEE Journal of Solid-State Circuits , vol.40 , Issue.7 , pp. 1549-1556
    • von Arnim, K.1
  • 48
    • 0348233280 scopus 로고    scopus 로고
    • A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
    • Dec
    • B. Murmann, and B. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification," IEEE Journal of Solid-State Circuits, Vol. 38, no. 12, pp. 2040-2050, Dec. 2003.
    • (2003) IEEE Journal of Solid-State Circuits , vol.38 , Issue.12 , pp. 2040-2050
    • Murmann, B.1    Boser, B.2
  • 49
    • 0035693616 scopus 로고    scopus 로고
    • A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm2 with mixed-signal chopping and calibration
    • Dec
    • H. van der Ploeg et al., "A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm2 with mixed-signal chopping and calibration," IEEE Journal of Solid-State Circuits, Vol. 36, no. 12, pp. 1859-1867, Dec. 2001.
    • (2001) IEEE Journal of Solid-State Circuits , vol.36 , Issue.12 , pp. 1859-1867
    • van der Ploeg, H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.