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Volumn 40, Issue 7, 2005, Pages 1549-1555

Efficiency of body biasing in 90-nm CMOS for low-power digital circuits

Author keywords

Body biasing; CMOS digital integrated circuits; Zero temperature coefficient point

Indexed keywords

BANDWIDTH; DIODES; ELECTRIC POTENTIAL; FUNCTIONS; MICROPROCESSOR CHIPS; OVERCURRENT PROTECTION; SHORT CIRCUIT CURRENTS; SWITCHING;

EID: 22544440903     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.847517     Document Type: Conference Paper
Times cited : (41)

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    • S.-F. Huang et al., "Scalability and biasing strategy for CMOS with active well bias," in Symp. VLSI Technology Dig. Tech. Papers, Jun. 2001, pp. 107-108.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.