A 0.5-V 1-Msps track-and-hold circuit with 60-dB SNDR

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 4, 2007, Pages 722-729

  Chatterjee, Shouri ^b,c   Kinget, Peter R ^a,d  

^a IEEE   (United States)

^b Columbia University ^*  (United States)

^c INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

^d Department of Earth and Environmental Sciences   (United States)

Author keywords

Analog integrated circuits; Body bias; Low voltage; Sample and hold; Track and hold

Indexed keywords

ANALOG INTEGRATED CIRCUITS; BODY BIAS; VOLTAGE BOOSTING;

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; ELECTRONIC CIRCUIT TRACKING; SIGNAL TO NOISE RATIO;

INTEGRATED CIRCUIT LAYOUT;

EID: 33947697782     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.892211     Document Type: Article

References (25)

1. The International Technology Roadmap for Semiconductors, ITRS 2005. 2005 [Online]. Available: http://public.itrs.net
2. B. Cook, A. Berny, A. Molnar, S. Lanzisera, and K. Pister, "An ultra-low power 2.4 GHz RF transceiver for wireless sensor networks in 0.13 μm CMOS with 400 mV supply and an integrated passive RX front-end," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2006. pp. 1460-1469.
3. S. Gambini and J. Rabaey, "A 1.5 MS/s 6-bit ADC with 0.5 V supply," in Proc. Asian Solid State Circuits Conf. (ASCC), 2006, pp. 47-50.
4. J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, "A 0.5-V 1-μw successive approximation ADC," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1261-1265, Jul. 2003.
5. S. Chatterjee, Y. Tsividis, and P. Kinget, "0.5-V analog circuit techniques and their application in OTA and filter design," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2373-2387, Dec. 2005.
6. S. Chatterjee and P. Kinget, "A 0.5-V 1-Msample/s 60-dB SNDR track-and-hold circuit," in Symp. VLSI Circuits Dig. Tech. Papers, 2006, pp. 56-57.
7. K. Gulati, M. S. Peng, A. Pulincherry, C. E. Munoz, M. Lugin, A. R. Bugeja, J. Li, and A. P. Chandrakasan, "A highly integrated CMOS analog baseband transceiver with 180 MSPS 13-bit pipelined CMOS ADC and dual 12-bit DACs," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1856-1866, Aug. 2006.
8. Q. Huang, "Low voltage and low power aspects of data converter design," in Proc. Eur. Solid State Circuits Conf. (ESSCIRC), 2000, pp. 29-35.
9. T. Cho and P. Gray, "A 10 b, 20 Msample/s, 35 mW, pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, Mar. 1995.
10. J.-T. Wu, Y.-H. Chang, and K. L. Chang, "1.2 V CMOS switchedcapacitor circuits," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 1996, pp. 388-389.
11. T. Brooks, D. Robertson, D. Kelly, A. D. Muro, and S. Harston, "A cascaded sigma-delta pipeline A/D converter with 1.25 MHZ signal bandwidth and 89 dB SNR," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1896-1906, Dec. 1997.
12. J. Steensgaard, "Bootstrapped low-voltage analog switches," in IEEE Int. Symp. Circuits and Systems (ISCAS), 1999, vol. 2, pp. 29-32.
13. A. Abo and P. Gray, "A 1.5-V, 10 bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
14. M. Dessouky and A. Kaiser, "A 1-V 1-mW digital-audio AS modulator with 88-dB dynamic range using local switch bootstrapping," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2000, pp. 13-16.
15. U. Moon, G. Temes, E. Bidari, M. Keskin, L. Wu, J. Steensgaard, and F. Maloberti, "Switched-capacitor circuit techniques in submicron low-voltage CMOS," in Proc. 6th Int. Conf. VLSI and CAD, 1999, pp. 349-358.
16. J. Crols and M.Steyaeit, "Switched-opamp: An approach to realize full CMOS switched-capacitor circuits at very low power-supply voltages," IEEE J. Solid-State Circuits, vol. 29, no. 8, pp. 936-942, Aug. 1994.
17. M. Ishikawa and T. Tsukahara, "An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wideband S/H," IEEE J. Solid-State Circuits, vol. 24, no. 12, pp. 1485-1491, Dec. 1989.
18. M. Nayebi and B. A. Wooley, "A 10-bit video BiCMOS track-and-hold amplifier," IEEE J. Solid-State Circuits, vol. 24, no. 12, pp. 1507-1516, Dec. 1989.
19. S. Narendra, J. Tschanz, J. Hofsheier, B. Bloechel, S. Vangal, Y. Hoskote, S. Tang, D. Somasekhar, A. Keshavarzi, V. Erraguntla, G. Dermer, N. Borkar, S. Borkar, and V. De, "Ultra-low voltage circuits and processor in 180 nm to 90 nm technologies with a swapped-body biasing technique," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2004, pp. 156-157.
20. J. H. Fischer, "Noise sources and calculation techniques for switched capacitor filters," IEEE J. Solid-State Circuits, vol. 17, no. 8, pp. 742-752, Aug. 1982.
21. L. Toth, I. Yusim, and K. Suyama, "Noise analysis of ideal switched-capacitor networks," IEEE Trans. Circuits Syst. I, Fundam. Theory Applicat., vol. 46, no. 3, pp. 349-363, Mar. 1999.
22. R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing. New York: Wiley, 1986, pp. 500-513.
23. R. Schreier, J. Silva, J. Steensgaard, and G. Temes, "Design- oriented estimation of thermal noise in switched-capacitor circuits," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 11, pp. 2358-2368, Nov. 2005.
24. P. Vorenkamp and J. P. M. Verdaasdonk, "Fully bipolar 120-MSample/s 10-b track-and-hold circuit," IEEE J. Solid-State Circuits, vol. 27, no. 7, pp. 988-992, Jul. 1992.
25. M.-J. Chen, J.-S. Ho, T.-H. Huang, C.-H. Yang, Y.-N. Jou, and T. Wu, "Back-gate forward bias method for low-voltage CMOS digital circuits," IEEE Trans. Electron Devices, vol. 43, no. 6, pp. 904-910, Jun. 1996.