A 0.5V 8bit 10Msps pipelined ADC in 90nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 202-203

  Shen, Junhua ^a   Kinget, Peter ^a  

^a Columbia University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; SOFTWARE PROTOTYPING; SWITCHES;

CASCADED SAMPLING TECHNIQUE; CONVERTER PROTOTYPE;

ANALOG TO DIGITAL CONVERSION;

EID: 39749150524     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342715     Document Type: Conference Paper

References (2)

1. "The International Technology Roadmap for Semiconductors'', http://public.itrs.net, 2005.
2. S. Narendra et al., "Ultra-low voltage circuits and processor in 180 nm to 90 nm technologies with a swapped-body biasing technique," in IEEE ISSCC. Feb. 2004, pp. 156-157.