A 0.5 v 900 MHz CMOS receiver front end

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 228-229

  Stanić, Nebojša ^a   Kinget, Peter ^a   Tsividis, Yannis ^a  

^a Columbia University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; ENERGY DISSIPATION; SIGNAL RECEIVERS;

CONVERSION GAIN; DOWNCONVERSION MIXERS; VOLTAGE BOOSTING;

CMOS INTEGRATED CIRCUITS;

EID: 34547301965     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S. Chatterjee, Y. Tsividis, and P. Kinget, "0.5-V Analog Circuit Techniques and their Application in OTA and Filter Design," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2373-2387, Dec. 2005.
2. M. Harada, T. Tsukahara, J. Kodate, A. Yamagishi, and J. Yamada, "2-GHz RF Front-end Circuits in CMOS/SIMOX Operating at an Extremely Low Voltage of 0.5V," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 2000-2004, Dec. 2000.
3. S. Hyvonen, K. Bhatia, and E. Rosenbaum, "An ESD-Protected, 2.45/5.25-GHz Dual-Band CMOS LNA with Series LC Loads and a 0.5-V supply," Proc. Radio Frequency Integrated Circuits Symposium, pp. 43;16, June 2005.
4. "The International Technology Roadmap for Semiconductors," http://public.itrs.net, 2004.
5. E. Klumperink, S. Louwsma, G. Wienk, and B. Nauta, "A CMOS Switched Transconductor Mixer," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1231-1240, Aug. 2004.