A wide power-supply range (0.5V-to-1.3V) wide tuning range (500 MHz-to-8 GHz) all-static CMOS AD PLL in 65nm SOI

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 172-173

  Rylyakov, A V ^a   Tierno, J A ^a   English, G J ^b   Friedman, D ^a   Meghelli, M ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; JITTER; PHASE NOISE; POWER SUPPLY CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS; TUNING;

PERIOD JITTER; PROGRAMMABLE LOOP FILTERS; TUNING RANGE;

PHASE LOCKED LOOPS;

EID: 34548858160     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373349     Document Type: Conference Paper

References (6)

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