Effects of interface states and positive charges on NBTI in silicon-oxynitride p-MOSFETs

IEEE Transactions on Device and Materials Reliability

Volumn 8, Issue 1, 2008, Pages 14-21

  Wang, Yangang ^a  

^a LIVERPOOL JOHN MOORES UNIVERSITY   (United Kingdom)

Author keywords

Degradation; Hole traps; Interface states; Negative bias temperature instability (NBTI); Oxynitride; p MOSFETs; Positive charges (PCs); Recovery; Reliability; Threshold voltage

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CHARGE; HOLE TRAPS; RELIABILITY; SILICON; TEMPERATURE MEASUREMENT; THRESHOLD VOLTAGE;

INTERFACE STATES; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); POSITIVE CHARGES; RECOVERY DYNAMICS;

MOSFET DEVICES;

EID: 40549122008     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2007.914015     Document Type: Article

References (34)

1. K. O. Jeppson and C. M. Svensson, "Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices," J. Appl. Phys., vol. 48, no. 5, pp. 2004-2014, May 1977.
2. C. E. Blat, E. H. Nicollian, and E. H. Poindexter, "Mechanism of negative bias-temperature instability," J. Appl. Phys., vol. 69, no. 3, pp. 1712-1720, Feb. 1991.
3. D. K. Schroder and J. A. Babcock, "Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing," J. Appl. Phys., vol. 94, no. 1, pp. 1-18, Jul. 2003.
4. S. S. Tan, T. P. Chen, C. H. Ang, and L. Chan, "Atomic modeling of nitrogen neighboring effect on negative bias temperature instability of pMOSFETs," IEEE Electron Device Lett., vol. 25, no. 7, pp. 504-506, Jul. 2004.
5. y interfaces," Appl. Phys. Lett., vol. 81, no. 10, pp. 1818-1820, Sep. 2002.
6. G. Chen, M. F. Li, C. H. Ang, J. Z. Zheng, and D. L. Kwong, "Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling," IEEE Electron Device Lett., vol. 23, no. 12, pp. 734-736, Dec. 2002.
7. B. Kaczer, V. Arkhipov, R. Degraeve, N. Collaert, G. Groeseneken, and M. Goodwin, "Temperature dependence of the negative bias temperature instability in the framework of dispersive transport," Appl. Phys. Lett., vol. 86, no. 14, p. 143 506, 2005.
8. M. Houssa, M. Aoulaiche, S. De Gendt, G. Groeseneken, M. M. Heyns, and A. Stesmans, "Reaction-dispersive proton transport model for negative bias temperature instabilities," Appl. Phys. Lett., vol. 86, no. 9, p. 093 506, 2005.
9. L. Tsetseris, X. J. Zhou, D. M. Fleetwood, R. D. Schrimpf, and S. T. Pantelides, "Physical mechanisms of negative-bias temperature instability," Appl. Phys. Lett., vol. 86, no. 14, p. 142 103, 2005.
10. D. S. Ang and K. L. Pey, "Evidence for two distinct positive trapped charge components in NBTI stressed p-MOSFETs employing ultrathin CVD silicon nitride gate dielectric," IEEE Electron Device Lett., vol. 25, no. 9, pp. 637-639, Sep. 2004.
11. V. Huard, M. Denais, and C. Parthasarathy, "NBTI degradation: From physical mechanisms to modelling," Microelectron. Reliab., vol. 46, no. 1, pp. 1-23, Jan. 2006.
12. S. Mahapatra, P. B. Kumar, and M. A. Alam, "Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs," IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1371-1379, Sep. 2004.
13. N. K. Jha and V. R. Rao, "A new oxide trap-assisted NBTI degradation model," IEEE Electron Device Lett., vol. 26, no. 9, pp. 687-689, Sep. 2005.
14. S. Tsujikawa and J. Yugami, "Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics," IEEE Trans. Electron Devices, vol. 53, no. 1, pp. 51-55, Jan. 2006.
15. V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan, "Impact of negative bias temperature instability on digital circuit reliability," Microelectron. Reliab., vol. 45, no. 1, pp. 31-38, Jan. 2005.
16. M. Denais, A. Bravaix, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, Y. R. Tauriac, and N. Revil, "On-the-fly characterization of NBTI in ultrathin gate oxide PMOSFETs," in IEDM. Tech. Dig., 2004, pp. 109-112.
17. M. Houssa, M. Aoulaiche, J. L. Autran, C. Parthasarathy, N. Revil, and E. Vincent, "Modeling negative bias temperature instabilities in hole channel metal-oxide-semiconductor field effect transistors with ultra-thin gate oxide layers," J. Appl. Phys., vol. 95, no. 5, pp. 2786-2791, Mar. 2004.
18. M. A. Alam and S. Mahapatra, "A comprehensive model of PMOS NBTI degradation," Microelectron. Reliab., vol. 45, no. 1, pp. 71-81, Jan. 2005.
19. M. Denais, V. Huard, C. Parthasarathy, G. Ribes, F. Perrier, N. Revil, and A. Bravaix, "Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide," IEEE Trans. Device Mater. Rel., vol. 4, no. 4, pp. 715-722, Dec. 2004.
20. 2 interface," IEEE Electron Device Lett., vol. 26, no. 8, pp. 572-574, Aug. 2005.
21. K. Watanabe, A. Teramoto, R. Kuroda, S. Sugawa, and T. Ohmi, "Examination of degradation mechanism due to negative bias temperature stress from a perspective of hole energy for accurate lifetime prediction," Microelectron. Reliab., vol. 47, no. 2/3, pp. 409-418, Feb./Mar. 2007.
22. J. R. Brews, "Subthreshold behavior of uniformly and nonuniformly doped long-channel MOSFET," IEEE Trans. Electron Devices, vol. ED-26, no. 9, pp. 1282-1291, Sep. 1979
23. C. H. Tan, M. Z. Xu, and Y. Y. Wang, "Application of the difference subthreshold swing analysis to study generation interface trap in MOS structures due to Fowler-Nordheim aging," IEEE Electron Device Lett., vol. 15, no. 7, pp. 257-259, Jul. 1994.
24. P. J. McWhorter and P. S. Winokur, "Simple technique for separating the effects of interface traps and trapped-oxide charge in metal-oxide- semiconductor transistors," Appl. Phys. Lett., vol. 48, no. 2, pp. 133-135, Jan. 1986.
25. B. Jun, D. M. Fleetwood, R. D. Schrimpf, X. Zhou, E. J. Montes, and S. Cristoloveanu, "Charge separation techniques for irradiated pseudoMOS SOI transistors," IEEE Trans. Nucl. Sci., vol. 50, no. 6, pp. 1891-1895, Dec. 2003.
26. J. F. Zhang, C. Z. Zhao, A. H. Chen, G. Groeseneken, and R. Degraeve, "Hole-traps in silicon dioxides-Part I: Properties," IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1267-1273, Aug. 2004.
27. D. S. Ang, S. Wang, and C. H. Ling, "Evidence of two distinct degradation mechanisms from temperature dependence of negative bias stressing of the ultrathin gate p-MOSFET," IEEE Electron Device Lett., vol. 26, no. 12, pp. 906-908, Dec. 2005.
28. D. S. Ang and S. Wang, "On the non-Arrhenius behavior of negative-bias temperature instability," Appl. Phys. Lett., vol. 88, no. 9, p. 093 506, 2006.
29. G. Chen, K. Y. Chuah, M. F. Li, D. S. H. Chan, C. H. Ang, J. Z. Zheng, Y. Jin, and D. L. Kwong, "Dynamic NBTI of PMOS transistors and its impact on device lifetime," in Proc. Int. Rel. Phys. Symp., 2003, pp. 196-202.
30. T. Yang, M. F. Li, C. Shen, C. H. Ang, C. X. Zhu, Y. C. Yeo, G. Samudra, S. C. Rustagi, M. B. Yu, and D. L. Kwong, "Fast and slow dynamic NBTI components in p-MOSFET with SiON dielectric and their impact on device life-time and circuit application," in VLSI Symp. Tech. Dig., 2005, pp. 92-93.
31. 2 and high-k dielectrics)," in Proc. IRW Final Rep., 2004, pp. 1-3.
32. D. J. DiMaria and E. Cartier, "Mechanism for stress-induced leakage currents in thin silicon dioxide films," J. Appl. Phys., vol. 78, no. 6, pp. 3883-3894, Sep. 1995.
33. D. J. DiMaria, E. Cartier, and D. Arnold, "Impact ionization, trap creation, degradation, and breakdown in silicon dioxide films on silicon," J. Appl. Phys., vol. 73, no. 7, pp. 3367-3384, Apr. 1993.
34. 2," Phys. Rev. B, Condens. Matter, vol. 57, no. 16, pp. 10030-10034, Apr. 1998.