A 14b 100MS/S digitally self-calibrated pipelined ADC in 0.13μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Bogner, Peter ^a   Kuttner, Franz ^a   Kropf, Claus ^a   Hartig, Thomas ^a   Burian, Markus ^a   Eul, Hermann ^b  

^a INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; GAIN MEASUREMENT; PIPELINE PROCESSING SYSTEMS;

CHARGE COMPENSATION; CMOS PROCESS; DIGITAL CALIBRATION; MATCHING ERRORS;

ANALOG TO DIGITAL CONVERSION;

EID: 33845653388     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. I. Galton, "Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters" IEEE Trans. Circ. Syst. II, vol. 47, no. 3, pp. 185-196, Mar., 2000.
2. H. Liu et al., "A 15b 20MS/s CMOS Pipelined ADC with Digital Background Calibration," ISSCC Dig. Tech. Papers, pp. 454-455, Feb., 2004.
3. P. Bogner "A 28mW 10b 80MS/s Pipelined ADC in 0.13μm CMOS" IEEE Int. Symp. Circuits and Sytems, vol. 1, pp. 17-20, May, 2004.