A new multilevel framework for large-scale interconnect-driven floorplanning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 2, 2008, Pages 286-294

  Chen, Tung Chieh ^a,b   Chang, Yao Wen ^a,b   Lin, Shyh Chang ^c  

^a IEEE

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^c SpringSoft Inc   (Taiwan)

Author keywords

Floorplanning; Multilevel framework; Partitioning; Physical design; Simulated annealing (SA)

Indexed keywords

COARSENING; CROSSTALK; FLOORS; GLOBAL OPTIMIZATION; MICROELECTRONICS; SIMULATED ANNEALING;

FLOORPLANNING; MULTILEVEL FRAMEWORK; PARTITIONING; PHYSICAL DESIGN;

INTERCONNECTION NETWORKS;

EID: 38649107025     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.907065     Document Type: Conference Paper

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