Corner block list: An effective and efficient topological representation of non-slicing floorplan

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 8-12

  Hong, Xianlong ^a   Huang, Gang ^a   Cai, Yici ^a   Gu, Jiangchun ^a   Dong, Sheqin ^a   Cheng, Chung Kuan ^b   Gu, Jun ^c  

^a TSINGHUA UNIVERSITY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; OPTIMIZATION; SIMULATED ANNEALING; TOPOLOGY; ALGORITHMS; BENCHMARKING; C (PROGRAMMING LANGUAGE); COMPUTER WORKSTATIONS; INTEGRATED CIRCUIT LAYOUT; THEOREM PROVING; VLSI CIRCUITS;

BLOCK BASED; BLOCK SIZES; BUILDING BLOCKES; CORNER BLOCK LISTS; FLOORPLAN ALGORITHMS; LINEAR TIME; SIMULATED ANNEALING TECHNIQUES; TOPOLOGICAL REPRESENTATION;

COMPUTER AIDED DESIGN;

BLOCK PLACEMENT ALGORITHM; CORNER BLOCK LIST; NONSLICING FLOORPLAN;

EID: 0034481271     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896442     Document Type: Conference Paper

References (7)

1. D.F.Wong & C.L.Liu, "Anew algorithm for floorplan design". In: Proc. of 23 ACM/IEEE Design Automation Conference, 101-107, 1986.
2. H. Onodera, Y.Taniguychi & K.Tamaru, " Branch and bound placement for building block layout" in: Proc. 28th ACM/IEEE Design Automation Conference, 423-439, 1991.
3. H. Murata, K. Fujiyoshi, S.Nakatake, & Y. Kajitani, " Rectangle-packing-based module placement", in: Proc. of International Conference on Computer Aided Design, 472 -479. 1995.
4. T.Tahahashi, " An algorithm for finding a maximum-weight decreasing sequence in a permutation, motivated by rectangle packing problem", Technical report of IEICE, vol. VLD 96, no.201, 31-35, 1996.
5. S.Nakatake, H. Murata, K. Fujiyoshi, Y. Kajitani, "Module placement on BSG-structure and IC layout application" in: Proc. of International Conference on Computer Aided Design, 484-490, 1996.
6. P.N.Guo, C.K.Cheng, " An O-tree representation of non-slicing floorplan and its applications", in: ACM/IEEE Design Automation Conference, 1999.
7. S.Kirkpatrick et al. "Optimization by simulated annealing, " Science, vol. 220, 671-680, 1983.