Module placement on BSG-structure and IC layout applications

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 484-491

  Nakatake, Shigetoshi ^a   Fujiyoshi, Kunihiro ^a   Murata, Hiroshi ^a   Kajitani, Yoji ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; SIMULATED ANNEALING;

BOUNDED SLICELINE GRID (BSG) STRUCTURE; MODULE PLACEMENT;

ELECTRONICS PACKAGING;

EID: 0030408582     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)