Twin binary sequences: A nonredundant representation for general nonslicing floorplan

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 4, 2003, Pages 457-469

  Young, Evangeline F Y ^a   Chu, Chris C N ^b   Shen, Zion Cien ^b  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b Iowa State University of Science and Technology   (United States)

Author keywords

Computer aided design; Floorplanning; Non slicing; Representation; Very large scale integration

Indexed keywords

BINARY SEQUENCES; ELECTRIC NETWORK TOPOLOGY; ESTIMATION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; RECURSIVE FUNCTIONS; TREES (MATHEMATICS); VLSI CIRCUITS;

BOUNDED-SLICELINE GRID; CORNER BLOCK LIST; MOSAIC FLOORPLAN; NONSLICING FLOORPLAN;

COMPUTER AIDED DESIGN;

EID: 0037387688     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.809651     Document Type: Article

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