-
1
-
-
0018618108
-
A parametric study of power MOSFETS
-
San Diego, CA
-
C. Hu, "A parametric study of power MOSFETS," in Proc. IEEE Power Electron. Spec. Conf. Rec., San Diego, CA, 1979, pp. 385-395.
-
(1979)
Proc. IEEE Power Electron. Spec. Conf. Rec
, pp. 385-395
-
-
Hu, C.1
-
2
-
-
0004179432
-
Semiconductor power devices with alternating conductivity type high-voltage breakdown regions,
-
U.S. Patent 5 216275, Jun. 1
-
X.-B. Chen, "Semiconductor power devices with alternating conductivity type high-voltage breakdown regions," U.S. Patent 5 216275, Jun. 1, 1993.
-
(1993)
-
-
Chen, X.-B.1
-
3
-
-
0032256942
-
A new generation of high voltage MOSFETs breaks the limit line of silicon
-
G. Deboy, M. Marz, J. Stengl, J. Tihani, and H. Weber, "A new generation of high voltage MOSFETs breaks the limit line of silicon," in IEDM Tech. Dig., 1998, pp. 683-685.
-
(1998)
IEDM Tech. Dig
, pp. 683-685
-
-
Deboy, G.1
Marz, M.2
Stengl, J.3
Tihani, J.4
Weber, H.5
-
4
-
-
4944221738
-
2 600 V-class superjunction MOSFET
-
2 600 V-class superjunction MOSFET," in Proc. ISPSD, 2004, pp. 459-462.
-
(2004)
Proc. ISPSD
, pp. 459-462
-
-
Saito, W.1
Omura, L.2
Aida, S.3
Koduki, S.4
Izumisawa, M.5
Yoshioka, H.6
Ogura, T.7
-
5
-
-
0042515318
-
200 V multi RESURF trench MOSFET (MR-TMOS)
-
T. Kurosaki, H. Shishido, M. Kitada, K. Oshima, S. Kunori, and A. Sugai, "200 V multi RESURF trench MOSFET (MR-TMOS)," in Proc. ISPSD, 2003, pp. 211-214.
-
(2003)
Proc. ISPSD
, pp. 211-214
-
-
Kurosaki, T.1
Shishido, H.2
Kitada, M.3
Oshima, K.4
Kunori, S.5
Sugai, A.6
-
6
-
-
4944245536
-
Design of a 200 V super junction MOSFET with n-buffer regions and its fabrication by trench filling
-
Y. Hattori, K. Nakashima, M. Kuwahara, T. Yoshida, S. Yamauchi, and H. Yamaguchi, "Design of a 200 V super junction MOSFET with n-buffer regions and its fabrication by trench filling," in Proc. ISPSD, 2004, pp. 189-192.
-
(2004)
Proc. ISPSD
, pp. 189-192
-
-
Hattori, Y.1
Nakashima, K.2
Kuwahara, M.3
Yoshida, T.4
Yamauchi, S.5
Yamaguchi, H.6
-
7
-
-
0041939730
-
Low voltage super junction MOSFET simulation and experimentation
-
T. Henson and J. Cao, "Low voltage super junction MOSFET simulation and experimentation," in Proc. ISPSD, 2003, pp. 37-40.
-
(2003)
Proc. ISPSD
, pp. 37-40
-
-
Henson, T.1
Cao, J.2
-
8
-
-
4944241970
-
2 transistor formed by 25 MeV masked boron implantation
-
2 transistor formed by 25 MeV masked boron implantation," in Proc. ISPSD, 2004, pp. 455-458.
-
(2004)
Proc. ISPSD
, pp. 455-458
-
-
Rub, M.1
Bar, M.2
Deboy, G.3
Niedemostheide, F.-J.4
Schmitt, M.5
Schulze, H.-J.6
Willmeroth, A.7
-
9
-
-
0036045603
-
Manufacturing of high aspect-ratio p-n junctions using vapor phase doping for application in multi-resurf devices
-
C. Rochefort, R. van Dalen, N. Duhayon, and W. Vandervorst, "Manufacturing of high aspect-ratio p-n junctions using vapor phase doping for application in multi-resurf devices," in Proc. ISPSD, 2002, pp. 237-240.
-
(2002)
Proc. ISPSD
, pp. 237-240
-
-
Rochefort, C.1
van Dalen, R.2
Duhayon, N.3
Vandervorst, W.4
-
10
-
-
37749006016
-
-
R. Van Dalen and C. Rochefort, Vertical multi-RESURF MOSFETs exhibiting record low specific resistance, in IEDM Tech. Dig., 2003, pp. 31.1.1-31.1.4.
-
R. Van Dalen and C. Rochefort, "Vertical multi-RESURF MOSFETs exhibiting record low specific resistance," in IEDM Tech. Dig., 2003, pp. 31.1.1-31.1.4.
-
-
-
-
11
-
-
4944258347
-
First study on superjunction high-voltage transistors with n-columns formed by proton implantation and annealing
-
M. Rub, M. Bar, F. J. Niedernostheide, M. Schmitt, H. J. Schulze, and A. Willmeroth, "First study on superjunction high-voltage transistors with n-columns formed by proton implantation and annealing," in Proc. ISPSD, 2004, pp. 181-184.
-
(2004)
Proc. ISPSD
, pp. 181-184
-
-
Rub, M.1
Bar, M.2
Niedernostheide, F.J.3
Schmitt, M.4
Schulze, H.J.5
Willmeroth, A.6
-
12
-
-
4043096847
-
Practical superjunction MOSFET device performance under given process thermal cycles
-
Aug
-
H. M. Zhong, Y. C. Liang, G. S. Samudra, and X. Yang, "Practical superjunction MOSFET device performance under given process thermal cycles," Semicond. Sci. Technol., vol. 19, no. 8, pp. 987-996, Aug. 2004.
-
(2004)
Semicond. Sci. Technol
, vol.19
, Issue.8
, pp. 987-996
-
-
Zhong, H.M.1
Liang, Y.C.2
Samudra, G.S.3
Yang, X.4
-
13
-
-
0036803509
-
A simple technology for superjunction device fabrication: Polyflanked VDMOSFET
-
Oct
-
K. P. Gan, X. Yang, Y. C. Liang, G. S. Samudra, and Y. Liu, "A simple technology for superjunction device fabrication: Polyflanked VDMOSFET," IEEE Electron Device Lett., vol. 23, no. 10, pp. 627-629, Oct. 2002.
-
(2002)
IEEE Electron Device Lett
, vol.23
, Issue.10
, pp. 627-629
-
-
Gan, K.P.1
Yang, X.2
Liang, Y.C.3
Samudra, G.S.4
Liu, Y.5
-
14
-
-
1242310372
-
-
M. J. Lin, T. H. Lee, F. L. Chang, C. W. Liaw, and H. C. Cheng, Lateral superjunction reduced surface field structure for the optimization of breakdown and conduction characteristics in a high-voltage lateral double diffused metal oxide field effect transistor, Jpn. J. Appl. Phys. 1, Regul. Rap. Short Notes, 42, no. 12, pp. 7227-7231, Dec. 2003.
-
M. J. Lin, T. H. Lee, F. L. Chang, C. W. Liaw, and H. C. Cheng, "Lateral superjunction reduced surface field structure for the optimization of breakdown and conduction characteristics in a high-voltage lateral double diffused metal oxide field effect transistor," Jpn. J. Appl. Phys. 1, Regul. Rap. Short Notes, vol. 42, no. 12, pp. 7227-7231, Dec. 2003.
-
-
-
-
15
-
-
4344648932
-
SJ/RESURF LDMOST
-
Jul
-
S. G. Nassif-Khalil, Z. H. Li, and C. A. T. Salama, "SJ/RESURF LDMOST," IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1185-1191, Jul. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.7
, pp. 1185-1191
-
-
Nassif-Khalil, S.G.1
Li, Z.H.2
Salama, C.A.T.3
-
16
-
-
27744450918
-
CMOS compatible super junction LDMOST with N-buffer layer
-
P. Il-Yong and C. A. T. Salama, "CMOS compatible super junction LDMOST with N-buffer layer," in Proc. ISPSD, 2005, pp. 163-166.
-
(2005)
Proc. ISPSD
, pp. 163-166
-
-
Il-Yong, P.1
Salama, C.A.T.2
-
17
-
-
0041513434
-
170 V super junction - LDMOST in a 0.5 μm commercial CMOS/SOS technology
-
S. G. Nassif-Khalil and C. A. T. Salama, "170 V super junction - LDMOST in a 0.5 μm commercial CMOS/SOS technology," in Proc. ISPSD, 2003, pp. 228-231.
-
(2003)
Proc. ISPSD
, pp. 228-231
-
-
Nassif-Khalil, S.G.1
Salama, C.A.T.2
-
18
-
-
84961786713
-
Numerical study of partial-SOI LDMOSFET power devices
-
J. M. Park, T. Grasser, H. Kosina, and S. Selberherr, "Numerical study of partial-SOI LDMOSFET power devices," in Proc. ISPSD, 2001, pp. 114-117.
-
(2001)
Proc. ISPSD
, pp. 114-117
-
-
Park, J.M.1
Grasser, T.2
Kosina, H.3
Selberherr, S.4
-
19
-
-
0034297791
-
120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit
-
Oct
-
S. M. Xu, K. P. Gan, G. S. Samudra, Y. C. Liang, and J. K. O. Sin, "120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit," IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1980-1985, Oct. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.10
, pp. 1980-1985
-
-
Xu, S.M.1
Gan, K.P.2
Samudra, G.S.3
Liang, Y.C.4
Sin, J.K.O.5
-
20
-
-
0034822671
-
Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI
-
R. Ng, F. Udrea, K. Sheng, K. Ueno, G. A. J. Amaratunga, and M. Nishiura, "Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI," in Proc. ISPSD, 2001, pp. 395-398.
-
(2001)
Proc. ISPSD
, pp. 395-398
-
-
Ng, R.1
Udrea, F.2
Sheng, K.3
Ueno, K.4
Amaratunga, G.A.J.5
Nishiura, M.6
-
21
-
-
0036053618
-
150-V class superjunction power LDMOS transistor switch on SOI
-
M. A. Amberetu and C. A. T. Salama, "150-V class superjunction power LDMOS transistor switch on SOI," in Proc. ISPSD, 2002, pp. 101-104.
-
(2002)
Proc. ISPSD
, pp. 101-104
-
-
Amberetu, M.A.1
Salama, C.A.T.2
-
22
-
-
0037004053
-
The partial silicon-on-insulator technology for RE power LDMOSFET devices and on-chip microinductors
-
Dec
-
C. H. Ren, J. Cai, and Y. C. Liang, "The partial silicon-on-insulator technology for RE power LDMOSFET devices and on-chip microinductors," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2271-2278, Dec. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, Issue.12
, pp. 2271-2278
-
-
Ren, C.H.1
Cai, J.2
Liang, Y.C.3
-
23
-
-
37749038831
-
Process for device using partial SOI,
-
U.S. Patent 6 551937 B2, Apr. 22, 2003
-
J. Cai, C. H. Ren, R. Balasubramaniam, N. Balasubramaniam, and Y. C. Liang, "Process for device using partial SOI," U.S. Patent 6 551937 B2, Apr. 22, 2003.
-
-
-
Cai, J.1
Ren, C.H.2
Balasubramaniam, R.3
Balasubramaniam, N.4
Liang, Y.C.5
-
24
-
-
0035425002
-
Oxide-bypassed VDMOS (OBVDMOS): An alternative to superjunction high voltage MOS power devices
-
Aug
-
Y. C. Liang, K. P. Gan, and G. S. Samudra, "Oxide-bypassed VDMOS (OBVDMOS): An alternative to superjunction high voltage MOS power devices," IEEE Electron Device Lett., vol. 22, no. 8, pp. 407-409, Aug. 2001.
-
(2001)
IEEE Electron Device Lett
, vol.22
, Issue.8
, pp. 407-409
-
-
Liang, Y.C.1
Gan, K.P.2
Samudra, G.S.3
-
25
-
-
0242662121
-
Tunable oxide-bypassed trench gate MOSFET: Breaking the ideal superjunction MOSFET performance line at equal column width
-
Nov
-
X. Yang, Y. C. Liang, G. S. Samudra, and Y. Liu, "Tunable oxide-bypassed trench gate MOSFET: Breaking the ideal superjunction MOSFET performance line at equal column width," IEEE Electron Device Lett., vol. 24, no. 11, pp. 704-706, Nov. 2003.
-
(2003)
IEEE Electron Device Lett
, vol.24
, Issue.11
, pp. 704-706
-
-
Yang, X.1
Liang, Y.C.2
Samudra, G.S.3
Liu, Y.4
-
26
-
-
37749025627
-
Slanted oxide-bypassed superjunction power MOSFETs
-
Y. Chen, Y. C. Liang, and G. S. Samudra, "Slanted oxide-bypassed superjunction power MOSFETs," in Proc. IECON, 2006, pp. 2746-2750.
-
(2006)
Proc. IECON
, pp. 2746-2750
-
-
Chen, Y.1
Liang, Y.C.2
Samudra, G.S.3
-
27
-
-
33847406718
-
Methods of forming power semiconductor devices having tapered trench-based insulating regions therein,
-
U.S. Patent 6 365 462 B2, Apr. 2, 2002
-
B. J. Baliga, "Methods of forming power semiconductor devices having tapered trench-based insulating regions therein," U.S. Patent 6 365 462 B2, Apr. 2, 2002.
-
-
-
Baliga, B.J.1
-
28
-
-
85008010099
-
Effects of oxide-fixed charge on the break-down voltage of superjunction devices
-
Mar
-
S. Balaji and S. Karmalkar, "Effects of oxide-fixed charge on the break-down voltage of superjunction devices," IEEE Electron Device Lett., vol. 28, no. 3, pp. 229-231, Mar. 2007.
-
(2007)
IEEE Electron Device Lett
, vol.28
, Issue.3
, pp. 229-231
-
-
Balaji, S.1
Karmalkar, S.2
-
29
-
-
34547111057
-
Design of gradient oxide-bypassed superjunction power MOSFET devices
-
Jul
-
Y. Chen, Y. C. Liang, and G. S. Samudra, "Design of gradient oxide-bypassed superjunction power MOSFET devices," IEEE Trans. Power Electron., vol. 22, no. 4, pp. 1303-1310, Jul. 2007.
-
(2007)
IEEE Trans. Power Electron
, vol.22
, Issue.4
, pp. 1303-1310
-
-
Chen, Y.1
Liang, Y.C.2
Samudra, G.S.3
|