-
1
-
-
0032598936
-
Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET
-
P. M. Shenoy, A. Bhalla, and G. M. Dolny, "Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET," in Proc. IEEE ISPSD, 1999, pp. 99-102.
-
(1999)
Proc. IEEE ISPSD
, pp. 99-102
-
-
Shenoy, P.M.1
Bhalla, A.2
Dolny, G.M.3
-
2
-
-
0036803509
-
A simple technology for superjunction device fabrication: Polyflanked VDMOSFET
-
Oct.
-
K. P. Gan, X. Yang, Y. C. Liang, G. S. Samudra, and Y. Liu, "A simple technology for superjunction device fabrication: Polyflanked VDMOSFET," IEEE Electron Device Lett., vol. 23, pp. 627-629, Oct. 2002.
-
(2002)
IEEE Electron Device Lett.
, vol.23
, pp. 627-629
-
-
Gan, K.P.1
Yang, X.2
Liang, Y.C.3
Samudra, G.S.4
Liu, Y.5
-
3
-
-
0031251517
-
Theory of semiconductor superjunction devices
-
Oct.
-
T. Fujihira, "Theory of semiconductor superjunction devices," Jpn. J. Appl. Phys., pt. 1, vol. 36, no. 10, pp. 6254-6262, Oct. 1997.
-
(1997)
Jpn. J. Appl. Phys., Pt. 1
, vol.36
, Issue.10
, pp. 6254-6262
-
-
Fujihira, T.1
-
4
-
-
0032256942
-
A new generation of high voltage MOSFET's breaks the limit line of silicon
-
G. Deboy, M. Marz, J. Stengl, J. Tihani, and H. Weber, "A new generation of high voltage MOSFET's breaks the limit line of silicon," in IEDM Tech. Dig., 1998, pp. 683-685.
-
(1998)
IEDM Tech. Dig.
, pp. 683-685
-
-
Deboy, G.1
Marz, M.2
Stengl, J.3
Tihani, J.4
Weber, H.5
-
5
-
-
0032295957
-
Theory of a novel voltage-sustaining layer for power devices
-
Dec.
-
X.-B. Chen, P. A. Mawby, K. Board, and C. A. T. Salama, "Theory of a novel voltage-sustaining layer for power devices," Microelectron. J., vol. 29, pp. 951-1046, Dec. 1998.
-
(1998)
Microelectron. J.
, vol.29
, pp. 951-1046
-
-
Chen, X.-B.1
Mawby, P.A.2
Board, K.3
Salama, C.A.T.4
-
6
-
-
0032598956
-
COOLMOS™ - A new milestone in high voltage power MOS
-
L. Lorenz, G. Deboy, A. Knapp, and M. März, "COOLMOS™ - A new milestone in high voltage power MOS," in Proc. Int. Symp. Power Semiconductor Devices and IC's, 1999, pp. 3-10.
-
(1999)
Proc. Int. Symp. Power Semiconductor Devices and IC's
, pp. 3-10
-
-
Lorenz, L.1
Deboy, G.2
Knapp, A.3
März, M.4
-
7
-
-
0034449069
-
MDmesh™: Innovative technology for high voltage PowerMOSFET's
-
M. Saggio, D. Fagone, and S. Musumeci, "MDmesh™: Innovative technology for high voltage PowerMOSFET's," in Proc. Int. Symp. Power Semiconductor Devices and IC's, 2000, pp. 65-68.
-
(2000)
Proc. Int. Symp. Power Semiconductor Devices and IC's
, pp. 65-68
-
-
Saggio, M.1
Fagone, D.2
Musumeci, S.3
-
8
-
-
0034449620
-
Experimental results and simulation analysis of 250 V super trench power MOSFET (STM)
-
T. Nitta, T. Minato, M. Yano, A. Uenisi, M. Harada, and S. Hine, "Experimental results and simulation analysis of 250 V super trench power MOSFET (STM)," in Proc. Int. Symp. Power Semiconductor Devices and IC's, 2000, pp. 77-80.
-
(2000)
Proc. Int. Symp. Power Semiconductor Devices and IC's
, pp. 77-80
-
-
Nitta, T.1
Minato, T.2
Yano, M.3
Uenisi, A.4
Harada, M.5
Hine, S.6
-
9
-
-
0034835108
-
Ultra-high voltage device termination using the 3D RESURF (Super-Junction) concept - Experimental demonstration at 6.5 kV
-
F. Udrea, T. Trajkovic, J. Thomson, L. Coulbeck, P. R. Waind, G. A. J. Amaratunga, and P. Taylor, "Ultra-high voltage device termination using the 3D RESURF (Super-Junction) concept - Experimental demonstration at 6.5 kV," in Proc. Int. Symp. Power Semiconductor Devices and IC's, 2001, pp. 129-132.
-
(2001)
Proc. Int. Symp. Power Semiconductor Devices and IC's
, pp. 129-132
-
-
Udrea, F.1
Trajkovic, T.2
Thomson, J.3
Coulbeck, L.4
Waind, P.R.5
Amaratunga, G.A.J.6
Taylor, P.7
-
10
-
-
0034822670
-
Breaking the silicon limit using semi-insulating RESURF layers
-
R. van Dalen, C. Rochefort, and G. A. M. Hurkx, "Breaking the silicon limit using semi-insulating RESURF layers," in Proc. Int. Symp. Power Semiconductor Devices and IC's, 2001, pp. 391-394.
-
(2001)
Proc. Int. Symp. Power Semiconductor Devices and IC's
, pp. 391-394
-
-
Van Dalen, R.1
Rochefort, C.2
Hurkx, G.A.M.3
-
12
-
-
0036053620
-
2 680 V silicon superjunction MOSFET
-
2 680 V silicon superjunction MOSFET," in Proc. Int. Symp. Power Semiconductor Devices and IC's, 2002, pp. 241-244.
-
(2002)
Proc. Int. Symp. Power Semiconductor Devices and IC's
, pp. 241-244
-
-
Onishi, Y.1
Iwamoto, S.2
Sato, T.3
Nagaoka, T.4
Ueno, K.5
Fujihira, T.6
-
13
-
-
0034447093
-
Which is cooler, trench or multi-epitaxy?
-
T. Minato, T. Nitta, A. Uenisi, M. Yano, M. Harada, and S. Hine, "Which is cooler, trench or multi-epitaxy?," in Proc. Int. Symp. Power Semiconductor Devices and IC's, 2000, pp. 73-76.
-
(2000)
Proc. Int. Symp. Power Semiconductor Devices and IC's
, pp. 73-76
-
-
Minato, T.1
Nitta, T.2
Uenisi, A.3
Yano, M.4
Harada, M.5
Hine, S.6
-
14
-
-
0035425002
-
Oxide-bypassed VDMOS (OBVDMOS): An alternative to superjunction high voltage MOS power devices
-
Aug.
-
Y. C. Liang, K. P. Gan, and G. S. Samudra, "Oxide-bypassed VDMOS (OBVDMOS): An alternative to superjunction high voltage MOS power devices, " IEEE Electron Device Lett., vol. 22, pp. 407-409, Aug. 2001.
-
(2001)
IEEE Electron Device Lett.
, vol.22
, pp. 407-409
-
-
Liang, Y.C.1
Gan, K.P.2
Samudra, G.S.3
-
15
-
-
0036053619
-
Tunable oxide-bypassed VDMOS (OBVDMOS): Breaking the silicon limit for the second generation
-
Y. C. Liang, X. Yang, G. S. Samudra, K. P. Gan, and Y. Liu, "Tunable oxide-bypassed VDMOS (OBVDMOS): Breaking the silicon limit for the second generation," Proc. IEEE ISPSD, pp. 201-204, 2002.
-
(2002)
Proc. IEEE ISPSD
, pp. 201-204
-
-
Liang, Y.C.1
Yang, X.2
Samudra, G.S.3
Gan, K.P.4
Liu, Y.5
-
16
-
-
0003667588
-
-
Avant! Corp., Fremont, CA
-
TSUPREM-4 User's Manual, Avant! Corp., Fremont, CA, 1998.
-
(1998)
TSUPREM-4 User's Manual
-
-
-
17
-
-
0003667590
-
-
Avant! Corp., Fremont, CA
-
MEDICI 4.1 User's Manual, Avant! Corp., Fremont, CA, 1998.
-
(1998)
MEDICI 4.1 User's Manual
-
-
-
18
-
-
0024125262
-
Ultralow resistance, selectively suicided VDMOSFET's for high-frequency power switching applications fabricated using sidewall Oxide spacer technology
-
Dec.
-
K. Shenai, P. A. Piacente, R. Saia, C. S. Korman, W. Tantraporn, and B. J. Baliga, "Ultralow resistance, selectively suicided VDMOSFET's for high-frequency power switching applications fabricated using sidewall Oxide spacer technology," IEEE Trans. Electron Devices, vol. 35, p. 2459, Dec. 1988.
-
(1988)
IEEE Trans. Electron Devices
, vol.35
, pp. 2459
-
-
Shenai, K.1
Piacente, P.A.2
Saia, R.3
Korman, C.S.4
Tantraporn, W.5
Baliga, B.J.6
-
19
-
-
0026404796
-
A scaled CMOS-compatible smart power IC technology
-
S. L. Wong, M. J. Kim, J. C. Young, and S. Mukherjee, "A scaled CMOS-compatible smart power IC technology," in Proc. Int. Symp. Power Semiconductor Devices and IC's, 1991, pp. 51-55.
-
(1991)
Proc. Int. Symp. Power Semiconductor Devices and IC's
, pp. 51-55
-
-
Wong, S.L.1
Kim, M.J.2
Young, J.C.3
Mukherjee, S.4
-
20
-
-
84866204664
-
A 50 V smart power process with dielectric isolation by SIMOX
-
J. Weyers and H. Vogt, "A 50 V smart power process with dielectric isolation by SIMOX," in IEDM Tech. Dig., 1992, pp. 225-228.
-
(1992)
IEDM Tech. Dig.
, pp. 225-228
-
-
Weyers, J.1
Vogt, H.2
-
21
-
-
0004418847
-
A study on a high blocking voltage UMOS-FET with a double gate structure
-
Y. Baba, N. Matsuda, S. Yanagiya, S. Hiraki, and S. Yasuda, "A study on a high blocking voltage UMOS-FET with a double gate structure," in Proc. Int. Symp. Power Semiconductor Devices and IC's, 1992, pp. 300-302.
-
(1992)
Proc. Int. Symp. Power Semiconductor Devices and IC's
, pp. 300-302
-
-
Baba, Y.1
Matsuda, N.2
Yanagiya, S.3
Hiraki, S.4
Yasuda, S.5
-
22
-
-
0036683906
-
A high-density low on-resistance trench lateral power MOSFET with a trench bottom source contact
-
Aug.
-
N. Fujishima, A. Sugi, S. Kajiwara, K. Matsubara, Y. Nagayasu, and C. A. T. Salama, "A high-density low on-resistance trench lateral power MOSFET with a trench bottom source contact," IEEE Trans. Electron Devices, vol. 49, pp. 1462-1468, Aug. 2002.
-
(2002)
IEEE Trans. Electron Devices
, vol.49
, pp. 1462-1468
-
-
Fujishima, N.1
Sugi, A.2
Kajiwara, S.3
Matsubara, K.4
Nagayasu, Y.5
Salama, C.A.T.6
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