-
1
-
-
4344578376
-
Semiconductor power devices with alternating conductivity type high voltage breakdown regions
-
X. B. Chen, "Semiconductor power devices with alternating conductivity type high voltage breakdown regions," U.S. Patent 5 216 275, 1993.
-
(1993)
U.S. Patent 5 216 275
-
-
Chen, X.B.1
-
3
-
-
0032295957
-
Theory of a novel voltage sustaining layer for power devices
-
X. B. Chen, P. A. Mawby, K. Board, and C. A. T. Salama, "Theory of a novel voltage sustaining layer for power devices," J. Microelectron., vol. 29, pp. 1005-1011, 1998.
-
(1998)
J. Microelectron.
, vol.29
, pp. 1005-1011
-
-
Chen, X.B.1
Mawby, P.A.2
Board, K.3
Salama, C.A.T.4
-
4
-
-
0032598956
-
COOL-MOSTM - a new milestone in high voltage power MOS
-
L. Lorenz, G. Deboy, A. Knapp, and M. Marz, "COOL-MOSTM - a new milestone in high voltage power MOS," in Proc. ISPSD, 1999, pp. 3-10.
-
(1999)
Proc. ISPSD
, pp. 3-10
-
-
Lorenz, L.1
Deboy, G.2
Knapp, A.3
Marz, M.4
-
5
-
-
0032046247
-
The 3D RESURF double-gate MOSFET: A revolutionary power device concept
-
F. Udrea, A. Popescu, and W. I. Milne, "The 3D RESURF double-gate MOSFET: A revolutionary power device concept," Electron. Lett., vol. 34, pp. 808-809, 1998.
-
(1998)
Electron. Lett.
, vol.34
, pp. 808-809
-
-
Udrea, F.1
Popescu, A.2
Milne, W.I.3
-
6
-
-
0032318239
-
A new class of lateral power devices for HVICs based on 3D RESURF concept
-
F. Udrea, A. Popescu, and W. I. Milne, "A new class of lateral power devices for HVICs based on 3D RESURF concept," Proc. BCTM, pp. 187-190, 1998.
-
(1998)
Proc. BCTM
, pp. 187-190
-
-
Udrea, F.1
Popescu, A.2
Milne, W.I.3
-
7
-
-
0034291628
-
An analytical model for the 3D-RESURF effect
-
R. Ng, F. Udrea, and G. A. J. Amaratunga, "An analytical model for the 3D-RESURF effect," Solid State Electron., vol. 44, pp. 1753-1764, 2000.
-
(2000)
Solid State Electron.
, vol.44
, pp. 1753-1764
-
-
Ng, R.1
Udrea, F.2
Amaratunga, G.A.J.3
-
8
-
-
4344655557
-
Super junction LDMOST using an insulator substrate for power integrated circuits
-
S. G. Nassif-Khalil and C. A. T. Salama, "Super Junction LDMOST Using an Insulator Substrate for Power Integrated Circuits," U.S. Patent 101117, 698, 2002.
-
(2002)
U.S. Patent 101117
, vol.698
-
-
Nassif-Khalil, S.G.1
Salama, C.A.T.2
-
9
-
-
0041672257
-
Super junction LDMOST on silicon-on-sapphire substrate
-
Oct
-
S. G. Nassif-Khalil and C. A. T. Salama, "Super junction LDMOST on silicon-on-sapphire substrate," IEEE Trans. Electron Devices, vol. 50, pp. 1385-1991, Oct. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, pp. 1385-1991
-
-
Nassif-Khalil, S.G.1
Salama, C.A.T.2
-
10
-
-
0036053765
-
Super junction LDMOST in silicon-on-sapphire technology (SJMOS)
-
S. G. Nassif-Khalil and C. A. T. Salama, "Super junction LDMOST in silicon-on-sapphire technology (SJMOS)," in Proc. ISPSD, 2002, pp. 81-84.
-
(2002)
Proc. ISPSD
, pp. 81-84
-
-
Nassif-Khalil, S.G.1
Salama, C.A.T.2
-
11
-
-
0041513434
-
170 V super junction - LDMOST in a 0.5 μm commercial CMOS/SOS technology
-
S. G. Nassif-Khalil and C. A. T. Salama, "170 V super junction - LDMOST in a 0.5 μm commercial CMOS/SOS technology," in Proc. ISPSD, 2003, pp. 228-231.
-
(2003)
Proc. ISPSD
, pp. 228-231
-
-
Nassif-Khalil, S.G.1
Salama, C.A.T.2
-
12
-
-
0034822671
-
Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI
-
R. Ng, F. Udrea, K. Sheng, K. Ueno, G. Amaratunga, and M. Nishiura, "Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI," in Proc. ISPSD, 2001, pp. 395-398.
-
(2001)
Proc. ISPSD
, pp. 395-398
-
-
Ng, R.1
Udrea, F.2
Sheng, K.3
Ueno, K.4
Amaratunga, G.5
Nishiura, M.6
-
13
-
-
4344642938
-
Super junction/RESURF LDMOST (SJR-LDMOST) in junction-isolated technology
-
S. G. Nassif-Khalil and C. A. T. Salama, "Super junction/RESURF LDMOST (SJR-LDMOST) in junction-isolated technology," U.S. Patent application, 2003.
-
(2003)
U.S. Patent Application
-
-
Nassif-Khalil, S.G.1
Salama, C.A.T.2
-
14
-
-
0034449647
-
A review of RESURF technology
-
A. W. Ludikhuize, "A review of RESURF technology," in Proc. ISPSD, 2000, pp. 11-18.
-
(2000)
Proc. ISPSD
, pp. 11-18
-
-
Ludikhuize, A.W.1
-
15
-
-
0035444714
-
Optimal on-resistance versus breakdown voltage tradeoff in superjunction power devices: A novel analytical model
-
Nov
-
A. G. M. Strollo and E. Napoli, "Optimal on-resistance versus breakdown voltage tradeoff in superjunction power devices: a novel analytical model," IEEE Trans. Electron Devices, pp. 2010-2161, Nov. 2001.
-
(2001)
IEEE Trans. Electron Devices
, pp. 2010-2161
-
-
Strollo, A.G.M.1
Napoli, E.2
-
16
-
-
0032598936
-
Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET
-
P. M. Shenoy, A. Bhalla, and G. M. Dolny, "Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET," in Proc. ISPSD, 1999, pp. 99-102.
-
(1999)
Proc. ISPSD
, pp. 99-102
-
-
Shenoy, P.M.1
Bhalla, A.2
Dolny, G.M.3
-
17
-
-
0036053409
-
Extended (180 V) voltage in 0.6 μm thin-layer-SOI A-BCD3 technology on 1 μm BOX for display, automotive and consumer applications
-
A. W. Ludikhuize, J. A. van der Pol, A. Heringa, A. Padiy, E. R. Ooms, P. van Kessel, G. J. J. Hessels, M. J. Swanenberg, B. van Velzen, H. van der Vlist, J. H. H. A. Egbers, and M. Stoutjesdijk, "Extended (180 V) voltage in 0.6 μm thin-layer-SOI A-BCD3 technology on 1 μm BOX for display, automotive & consumer applications," in Proc. ISPSD, 2002, pp. 77-80.
-
(2002)
Proc. ISPSD
, pp. 77-80
-
-
Ludikhuize, A.W.1
van der Pol, J.A.2
Heringa, A.3
Padiy, A.4
Ooms, E.R.5
van Kessel, P.6
Hessels, G.J.J.7
Swanenberg, M.J.8
van Velzen, B.9
van der Vlist, H.10
Egbers, J.H.H.A.11
Stoutjesdijk, M.12
-
18
-
-
0026190412
-
A versatile 700/1200 V IC process for analog and switching applications
-
Oct
-
A. W. Ludikhuize, "A versatile 700/1200 V IC process for analog and switching applications," IEEE Trans. Electron Devices, vol. 38, pp. 1582-1589, Oct. 1991.
-
(1991)
IEEE Trans. Electron Devices
, vol.38
, pp. 1582-1589
-
-
Ludikhuize, A.W.1
-
19
-
-
4344709140
-
-
Power Semiconductor Devices: PWS Publishing
-
B. J. Baliga, Power Semiconductor Devices: PWS Publishing, 1996.
-
(1996)
-
-
Baliga, B.J.1
|