Lateral unbalanced Super Junction (USJ)/3D-RESURF for high breakdown voltage on SOI

IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)

Volumn , Issue , 2001, Pages 395-398

  Ng, R ^a   Udrea, F ^a   Sheng, K ^a   Ueno, K ^a   Amaratunga, G A J ^a   Nishiura, M ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC BREAKDOWN; POWER INTEGRATED CIRCUITS; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY;

UNBALANCED SUPER JUNCTION (USJ);

SEMICONDUCTOR JUNCTIONS;

EID: 0034822671     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. High voltage thin layer devices (Resurf Devices)
2. The effects of SIPOS passivation on DC and switching performance of high voltage MOS transistors
3. Novel silicon-on-insulator Mosfet for High Voltage Integrated Circuits
4. The effects of SIPOS passivation on DC and switching performance of high voltage MOS transistors
5. A new class of lateral power devices for HVIC based on the 3D-RESURF concept
6. The SD RESURF double gate MOSFET
7. Ultra-high voltage device termination using the SD-RESURF(SuperJunction) concept - Experimental demonstration at 6.5kV
8. Extension of RESURF principle to D1 power devices
9. Realization of high breakdown voltage (>700V) in thin SOI device
10. An analytical model of the 3D-RESURF effect
11. Simulated superior performances of semiconductor SuperJunction devices
12. Cool MOS. An important milestone towards a new power MOSFET generation