A simple technology for superjunction device fabrication: Polyflanked VDMOSFET

IEEE Electron Device Letters

Volumn 23, Issue 10, 2002, Pages 627-629

  Gan, Kian Paau ^b   Yang, Xin ^b   Liang, Yung C ^a,b,c   Samudra, Ganesh S ^a,b   Yong, Liu ^d  

^a IEEE   (United States)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

Power MOSFET; Superjunction device

Indexed keywords

SUPERJUNCTION DEVICE; VERTICAL DOUBLE DIFFUSED STRUCTURE;

COMPUTER SIMULATION; ELECTRIC BREAKDOWN; INTEGRATED CIRCUIT LAYOUT; MASKS; POWER INTEGRATED CIRCUITS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR JUNCTIONS;

MOSFET DEVICES;

EID: 0036803509     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2002.803770     Document Type: Article

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