-
1
-
-
0033281303
-
"Channel engineering for high-speed sub-1.0 V power supply deep sub-micron CMOS"
-
B. Cheng, R. Rao, and J. C. S. Woo, "Channel engineering for high-speed sub-1.0 V power supply deep sub-micron CMOS," in VLSI Symp. Tech. Dig., 1999, pp. 69-70.
-
(1999)
VLSI Symp. Tech. Dig.
, pp. 69-70
-
-
Cheng, B.1
Rao, R.2
Woo, J.C.S.3
-
2
-
-
0036712433
-
"Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications"
-
Sep
-
H. V. Deshpande, B. Cheng, and J. C. S. Woo, "Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications," IEEE Trans. Electron. Devices, vol. 49, no. 9, pp. 1558-1565, Sep. 2002.
-
(2002)
IEEE Trans. Electron. Devices
, vol.49
, Issue.9
, pp. 1558-1565
-
-
Deshpande, H.V.1
Cheng, B.2
Woo, J.C.S.3
-
3
-
-
0346707543
-
"Impact of lateral asymmetric channel doping on deep sub-micrometer mixed-signal device and circuit performance"
-
Dec
-
K. Narasimhulu, D. K. Sharma, and V. R. Rao, "Impact of lateral asymmetric channel doping on deep sub-micrometer mixed-signal device and circuit performance," IEEE Trans. Electron. Devices, vol. 50, no. 12, pp. 2481-2489, Dec. 2003.
-
(2003)
IEEE Trans. Electron. Devices
, vol.50
, Issue.12
, pp. 2481-2489
-
-
Narasimhulu, K.1
Sharma, D.K.2
Rao, V.R.3
-
4
-
-
0003233340
-
"Transistor design issues in integrating analog functions with high performance digital CMOS"
-
A. Chatterjee, K. Vasanth, D. T. Grider, M. Nandakumar, G. Pollack, R. Aggarwal, M. Rodder, and H. Shichijo, "Transistor design issues in integrating analog functions with high performance digital CMOS," in VLSI Symp. Tech. Dig., 1999, pp. 7-8.
-
(1999)
VLSI Symp. Tech. Dig.
, pp. 7-8
-
-
Chatterjee, A.1
Vasanth, K.2
Grider, D.T.3
Nandakumar, M.4
Pollack, G.5
Aggarwal, R.6
Rodder, M.7
Shichijo, H.8
-
5
-
-
0035691874
-
"Analog device design for low power mixed mode applications in deep sub-micron CMOS technology"
-
Dec
-
H. V. Deshpande, B. Cheng, and J. C. S. Woo, "Analog device design for low power mixed mode applications in deep sub-micron CMOS technology," IEEE Electron. Device Lett., vol. 22, no. 12, pp. 588-590, Dec. 2001.
-
(2001)
IEEE Electron. Device Lett.
, vol.22
, Issue.12
, pp. 588-590
-
-
Deshpande, H.V.1
Cheng, B.2
Woo, J.C.S.3
-
6
-
-
0033905094
-
"Oscillator phase noise: A tutorial"
-
Mar
-
T. H. Lee and A. Hajimiri, "Oscillator phase noise: A tutorial," IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326-336, Mar. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.3
, pp. 326-336
-
-
Lee, T.H.1
Hajimiri, A.2
-
7
-
-
49949124297
-
"Low frequency noise in MOS transistors - I Theory"
-
Sep
-
S. Christensson, I. Lundstrom, and C. Svensson, "Low frequency noise in MOS transistors - I Theory," Solid State Electron., vol. 23, no. 9, pp. 797-812, Sep. 1968.
-
(1968)
Solid State Electron.
, vol.23
, Issue.9
, pp. 797-812
-
-
Christensson, S.1
Lundstrom, I.2
Svensson, C.3
-
8
-
-
0021483220
-
"Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion - Influence of interface states"
-
Sep
-
G. Reimbold, "Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion - influence of interface states," IEEE Trans. Electron. Devices, vol. ED-31, no. 9, pp. 1190-1198, Sep. 1984.
-
(1984)
IEEE Trans. Electron. Devices
, vol.ED-31
, Issue.9
, pp. 1190-1198
-
-
Reimbold, G.1
-
9
-
-
84908155589
-
"Realization of sub 100 nm asymmetric channel MOSFETs with excellent short-channel performance and reliability"
-
B. Cheng, V. R. Rao, B. Ikegami, and J. C. S. Woo, "Realization of sub 100 nm asymmetric channel MOSFETs with excellent short-channel performance and reliability," in Proc. ESSDERC Tech. Dig., 1998, pp. 520-523.
-
(1998)
Proc. ESSDERC Tech. Dig.
, pp. 520-523
-
-
Cheng, B.1
Rao, V.R.2
Ikegami, B.3
Woo, J.C.S.4
-
10
-
-
22944479623
-
"Linearkink-noise suppression in partially depleted SOI using the twin-gate MOSFET configuration"
-
Jul
-
E. S. C. Claeys, N. Lukyanchikova, N. Garbar, and A. Smolanka, "Linearkink-noise suppression in partially depleted SOI using the twin-gate MOSFET configuration," IEEE Electron. Device Lett., vol. 26, no. 7, pp. 510-512, Jul. 2005.
-
(2005)
IEEE Electron. Device Lett.
, vol.26
, Issue.7
, pp. 510-512
-
-
Claeys, E.S.C.1
Lukyanchikova, N.2
Garbar, N.3
Smolanka, A.4
-
11
-
-
3943079319
-
"Pocket implantation effect on drain current flicker noise in analog nMOSFET devices"
-
Aug
-
J.-W. Wu, C.-C. Cheng, K.-L. Chiu, J.-C. Guo, W.-Y. Lien, C.-S. Chang, G.-W. Huang, and T. Wang, "Pocket implantation effect on drain current flicker noise in analog nMOSFET devices," IEEE Trans Electron. Devices, vol. 51, no. 8, pp. 1262-1266, Aug. 2004.
-
(2004)
IEEE Trans Electron. Devices
, vol.51
, Issue.8
, pp. 1262-1266
-
-
Wu, J.-W.1
Cheng, C.-C.2
Chiu, K.-L.3
Guo, J.-C.4
Lien, W.-Y.5
Chang, C.-S.6
Huang, G.-W.7
Wang, T.8
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