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Volumn 50, Issue 11-12, 2006, Pages 1705-1709

Degradation of 1/f noise in short channel MOSFETs due to halo angle induced VT non-uniformity and extra trap states at interface

Author keywords

Halo angle; Hot carrier effect; Interface trap density; Low frequency noise; Oxide trap density; Silicon; Silicon dioxide; Threshold voltage

Indexed keywords

ELECTRON TRAPS; INTERFACES (MATERIALS); SILICA; SILICON; THRESHOLD VOLTAGE;

EID: 33751205065     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2006.09.010     Document Type: Article
Times cited : (12)

References (20)
  • 2
    • 0035716617 scopus 로고    scopus 로고
    • A high density 0.1 μm CMOS technology using low k dielectric and Cu interconnect
    • Parihar S. A high density 0.1 μm CMOS technology using low k dielectric and Cu interconnect. IEDM Tech Digest December (2001) 249-252
    • (2001) IEDM Tech Digest , Issue.December , pp. 249-252
    • Parihar, S.1
  • 4
    • 0035472028 scopus 로고    scopus 로고
    • Optimum Halo structure for sub-0.10 μm CMOSFETs
    • Yeh Y.K., and Chou J.W. Optimum Halo structure for sub-0.10 μm CMOSFETs. IEEE Trans Electron Dev 48 October (2001) 2357-2362
    • (2001) IEEE Trans Electron Dev , vol.48 , Issue.October , pp. 2357-2362
    • Yeh, Y.K.1    Chou, J.W.2
  • 6
    • 0036529341 scopus 로고    scopus 로고
    • Linearity analysis and design optimization for 0.18 μm CMOS RF mixer
    • Li Q., and Yuan J.S. Linearity analysis and design optimization for 0.18 μm CMOS RF mixer. Proc Circuits, Dev Systems (2002) 112-118
    • (2002) Proc Circuits, Dev Systems , pp. 112-118
    • Li, Q.1    Yuan, J.S.2
  • 7
    • 0033280393 scopus 로고    scopus 로고
    • Transistor design issues in integrating analog functions with high performance digital CMOS
    • Chatterjee A., et al. Transistor design issues in integrating analog functions with high performance digital CMOS. Symp VLSI Tech Digest (1999) 147-148
    • (1999) Symp VLSI Tech Digest , pp. 147-148
    • Chatterjee, A.1
  • 8
    • 0035691874 scopus 로고    scopus 로고
    • Analog device design for low power mixed mode applications in deep sub micrometer CMOS technology
    • Deshpande H.V., et al. Analog device design for low power mixed mode applications in deep sub micrometer CMOS technology. IEEE Electron Dev Lett 22 July (2001) 588-590
    • (2001) IEEE Electron Dev Lett , vol.22 , Issue.July , pp. 588-590
    • Deshpande, H.V.1
  • 9
    • 0032276255 scopus 로고    scopus 로고
    • 0.12 μm raised gate/source/drain epitaxial channel n-MOS technology
    • Ohguo T., et al. 0.12 μm raised gate/source/drain epitaxial channel n-MOS technology. IEDM Tech Digest (1998) 927-930
    • (1998) IEDM Tech Digest , pp. 927-930
    • Ohguo, T.1
  • 11
    • 23944498418 scopus 로고    scopus 로고
    • Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs
    • Kumar D.V., Narasimhulu K., Reddy P.S., Shojaei M., Sharma D.K., Patil M.B., et al. Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs. IEEE Trans Electron Dev 52 7 July (2005)
    • (2005) IEEE Trans Electron Dev , vol.52 , Issue.7 July
    • Kumar, D.V.1    Narasimhulu, K.2    Reddy, P.S.3    Shojaei, M.4    Sharma, D.K.5    Patil, M.B.6
  • 12
    • 1942488204 scopus 로고    scopus 로고
    • Impact of post-oxidation annealing on low-frequency noise, threshold voltage and sub threshold swing of p-channel MOSFET
    • Ahsan A.K.M., and Schroder D.K. Impact of post-oxidation annealing on low-frequency noise, threshold voltage and sub threshold swing of p-channel MOSFET. IEEE Electron Dev Lett 25 April (2004) 211-213
    • (2004) IEEE Electron Dev Lett , vol.25 , Issue.April , pp. 211-213
    • Ahsan, A.K.M.1    Schroder, D.K.2
  • 13
    • 0025398785 scopus 로고
    • A unified model for flicker noise in metal oxide semiconductor field effect transistors
    • Hung K.K., Ko P.K., Hu C., and Cheng Y.C. A unified model for flicker noise in metal oxide semiconductor field effect transistors. IEEE Trans Electron Dev 37 March (1990) 654-665
    • (1990) IEEE Trans Electron Dev , vol.37 , Issue.March , pp. 654-665
    • Hung, K.K.1    Ko, P.K.2    Hu, C.3    Cheng, Y.C.4
  • 14
    • 0025434759 scopus 로고
    • A physics based MOSFET noise model for circuit simulators
    • Hung K.K., Ko P.K., Hu C., and Cheng Y.C. A physics based MOSFET noise model for circuit simulators. IEEE Trans Electron Dev 37 May (1990) 1323-1333
    • (1990) IEEE Trans Electron Dev , vol.37 , Issue.May , pp. 1323-1333
    • Hung, K.K.1    Ko, P.K.2    Hu, C.3    Cheng, Y.C.4
  • 15
    • 13644267935 scopus 로고    scopus 로고
    • Impact of channel carrier displacement and barrier height lowering on the low-frequency noise characteristics of surface-channel n-MOSFETs
    • Ahsan A.K.M., and Schroder D.K. Impact of channel carrier displacement and barrier height lowering on the low-frequency noise characteristics of surface-channel n-MOSFETs. Solid-State Electron 49 April (2005) 654-662
    • (2005) Solid-State Electron , vol.49 , Issue.April , pp. 654-662
    • Ahsan, A.K.M.1    Schroder, D.K.2
  • 16
    • 3943079319 scopus 로고    scopus 로고
    • Pocket implantation effect on drain current flicker noise in analog n-MOSFET devices
    • Wu J., et al. Pocket implantation effect on drain current flicker noise in analog n-MOSFET devices. IEEE Trans Electron Dev 51 August (2004) 1262-1265
    • (2004) IEEE Trans Electron Dev , vol.51 , Issue.August , pp. 1262-1265
    • Wu, J.1
  • 17
    • 0028549082 scopus 로고
    • The impact of device scaling on the current fluctuations in MOSFETs
    • Tsai M.H., and Ma T.P. The impact of device scaling on the current fluctuations in MOSFETs. IEEE Trans Electron Dev 41 November (1994) 2061-2068
    • (1994) IEEE Trans Electron Dev , vol.41 , Issue.November , pp. 2061-2068
    • Tsai, M.H.1    Ma, T.P.2
  • 18
    • 0033894377 scopus 로고    scopus 로고
    • MOSFET channel length: extraction and interpretation
    • Taur Y. MOSFET channel length: extraction and interpretation. IEEE Trans Electron Dev 47 January (2000) 160
    • (2000) IEEE Trans Electron Dev , vol.47 , Issue.January , pp. 160
    • Taur, Y.1
  • 19
    • 0036929393 scopus 로고    scopus 로고
    • A three-transistor threshold voltage model for halo processes
    • Rios R., et al. A three-transistor threshold voltage model for halo processes. IEDM Tech Digest (2002) 113-116
    • (2002) IEDM Tech Digest , pp. 113-116
    • Rios, R.1
  • 20
    • 0033877179 scopus 로고    scopus 로고
    • eff extraction techniques for MOS transistors with halo or pocket implants
    • eff extraction techniques for MOS transistors with halo or pocket implants. IEEE Electron Dev Lett 21 February (2000) 133
    • (2000) IEEE Electron Dev Lett , vol.21 , Issue.February , pp. 133
    • van Meer, H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.