Ultra-low standby power (U-LSTP) 65-nm node CMOS technology utilizing HfSiON dielectric and body-biasing scheme

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 218-219

  Kimizuka, N ^a   Yasuda, Y ^a   Iwamoto, T ^b   Yamamoto, I ^a   Takano, K ^a   Akiyama, Y ^a   Imai, K ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

Body bias; Fermi level pinning; HfSiON; LSTP

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC DEVICES; FERMI LEVEL; FIELD EFFECT TRANSISTORS; HAFNIUM COMPOUNDS; LEAKAGE CURRENTS;

BODY-BIASING SCHEME; HFSION DIELECTRIC; PFET; ULTRA-LOW STANDBY POWER (U-LSTP);

STANDBY POWER SERVICE;

EID: 33646230827     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469274     Document Type: Conference Paper

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