On characterizing performance of the cell broadband engine element interconnect bus

Proceedings - NOCS 2007: First International Symposium on Networks-on-Chip

Volumn , Issue , 2007, Pages 18-29

  Ainsworth, Thomas William ^a   Pinkston, Timothy Mark ^a  

^a University of Southern California   (United States)

Author keywords

Cell broadband engine; Element interconnect bus; Heterogeneous multicore; Interconnection networks; Network characterization; Network on chip; On chip network; Performance bottleneck

Indexed keywords

BANDWIDTH; COMPUTER SOFTWARE; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; SCALABILITY;

CELL BROADBAND ENGINE; ELEMENT INTERCONNECT BUS; HETEROGENEOUS MULTICORE; NETWORK CHARACTERIZATION; NETWORK-ON-CHIP; ON-CHIP NETWORKS; PERFORMANCE BOTTLENECK;

BROADBAND NETWORKS;

EID: 36348971705     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2007.34     Document Type: Conference Paper

References (46)

1. William J. Dally, "Interconnect limited VLSI architecture," in Proceedings of International Interconnect Technology Conference, pp 15-17, May 1999.
2. William J. Dally and Brian Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," in Proc. of the Design Automation Conf, pp 684-689, ACM, June 2001.
3. Luca Benini and Giovanni De Micheli, "Networks on Chip: A New SoC Paradigm," IEEE Computer, Volume 35, Issue 1, pp 70-80, January 2002.
4. Ahmed Hemani, Axel Jantsch, Shashi Kumar, Adam Postula, Johnny O'berg, Mikael Millberg, and Dan Lidqvist, "Network on a Chip: An Architecture for Billion Transitar Era," in Proc. of the IEEE NorChip Conference, Nov., 2000.
5. Marco Sgroi, M. Sheets, A. Mihal, Kurt Keutzer, Sharad Malik, Jan M. Rabaey, and Alberto L. Sangiovanni- Vincentelli, "Addressing the system-on-a-chip interconnect woes through communication-based design," in Proceedings of Design Automation Conference, pp 667-672, June 2001.
6. "IBM CoreConnect," Technical Report, www.chips.ibm.com/ products/powerpc/cores. 2000.
7. Kanishka Lahiri, Anand Raghunathan, and Ganesh Lakshminarayana, "LotteryBus: A New High-Performance Communication Architecture for System-on-Chip Designs," in Proc. of the Design Automation Conf, ACM, June 2001.
8. David Flynn, "AMBA: Enabling Reusable On-Chip Designs," IEEE Micro, pp 20-27, July/August 1997.
9. Rakesh Kumar, Victor Zyuban, and Dean~M. Tullsen, "Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads, and Scaling," in Proceedings of the International Symposium on Computer Architecture, IEEE Computer Society, June 2005.
10. Jian Liang, Sriram Swaminathan, and Russell Tessier, "aSoC: A Scalable, Singlechip Communications Architecture," in Int 7 Conference on Parallel Architectures and Compilation Techniques, pp 37-46, October 2000.
11. Pierre Guerrier and Alain Greiner, "A Generic Architecture for On-Chip Packet-Switched Interconnections," in Proceedings of the Design Automation and Test in Europe, pp 250-256, March 2000.
12. Adrijean Adriahantenaina, Herv 'e Charlery, Alain Greiner, Laurent Mortiez, and Cesar~Albenes Zeferino, "SPIN: A Scalable, Packet Switched, On-Chip Micro- Network," in Proceedings of the Design, Automation and Test in Europe Conference, March 2003.
13. Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen, Martti Forsell, Mikael Millberg, Johnny O'berg, Kari Tiensyrja, and Ahmed Hemani, "A Network on Chip Architecture and Design Methodology," in Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp 105-112, 2002.
14. Jacob Chang, Srivaths Ravi, and Anand Raghunathan, "FLEXBAR: A Crossbar Switching Fabric with Improved Performance and Utilization," in Proceedings of the IEEE CICC, pp 405-408, 2002.
15. A. Brinkmann, J. C. Niemann, I. Hehemann, D. Langen, M. Porrmann, and U. Ruckert, "On-chip Interconects for Next Generation Systems-on-Chips," in Proc. of the 15th Annual IEEE Int'l ASIC/SOC Conf., pp 211-215, Sept 2002.
16. Timothy Mark Pinkston and Jeonghee Shin, "Trends Toward On-Chip Networked Microsystems," in International Journal of High Performance Computing and Networking, Volume 3, Number 1, pp 3-18, December 2005.
17. Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio Gonzalez, and Jose Duato, "Efficient Interconnects for Clustered Microarchitectures," in Proceedings of 2002 International Conference on Parallel Architectures and Compilation Techniques, September 2002.
18. Aneesh Aggarwal and Manoj Franklin, "Hierarchical Interconnects for On-chip Clustering," in Proc. of Int'l Parallel and Distributed Processing Symposium, April 2002.
19. Shubhendu S. Mukherjee, Peter Bannon, Steven Lang, Aaron Spink, and David Webb, "The Alpha 21364 Network Architecture," in Proceedings of Hot Interconnects 9, pp 113-117, August 2001.
20. Gurindar S. Sohi, Scott E. Breach, and T. N. Vijaykumar, "Multiscalar Processors," in Proceedings of the 22nd Annual International Symposium on Computer Architecture, pp 414-425, June 1995.
21. Michael Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Paul Johnson, Jae-Wook Lee, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman Amarasinghe, and Anant Agarwal, "The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs," IEEE Micro, Volume 22, Issue 2, pp 25-35, March/April 2002.
22. Michael Bedford Taylor, Walter Lee, Saman P., Amarasinghe, and Anant Agarwal, "Scalar Operand Networks," IEEE Transactions on Parallel and Distributed Systems, Volume 16, Issue 2, February 2005.
23. Doug Berger, Steve Keckler, and the TRIPS Project Team, "Design and Implementation of the TRIPS EDGE Architecture," ISCA-32 Tutorial, pp 1-239, June 2005.
24. Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, and Stephen W. Keckler, "A design space evaluation of grid processor architectures," in Proceedings of the 34th Annual International Symposium on Microarchitecture, pages 40-51, December 2001.
25. H. Peter Hofstee, "Power Efficient Processor Architecture and the Cell Processor," in Proceedings of the Eleventh Int'l Symposium on High-Performance Computer Architecture, IEEE Computer Society, February 2005.
26. Kevin Krewell, "Sun's Niagara Pours on the Cores," Microprocessor Report, Vol. 18, No. 9, pp 1-3, Sept., 2004.
27. James M. Baker Jr., Brian Gold, Mark Bucciero, Sidney Bennett, Rajneesh Mahajan, Priyadarshini Ramachandran, and Jignesh Shah, "SCMP: A Single-Chip Message-Passing Parallel Computer," in the Journal of Supercomputing, Volume 30, pp 133-149, 2004.
28. Terry Tao Ye, Luca Benini, and Giovanni De Micheli, "Packetized On-Chip Interconnect Communication Analysis for MPSoC," in Proceedings of the Design, Automation and Test in Europe Conference, pp 344-349, March 2003.
29. Peter N. Glaskowsky, "IBM raises curtain on Power5," Microprocessor Report, Volume 17, Issue 10, pp 13-14, October 2003.
30. Joel M. Tendler, Steve Dodson, Steve Fields, Hung Lee, and Balaram Sinharoy, "POWER4 system microarchitecture," IBM Journal of Research and Development, Volume 46, Issue 1, pp 5-26, January 2002.
31. Seon Wook Kim, Chong-Liang Ooi, Il~Park, Rudolf Eigenmann, Babak Falsafi, and T. N. Vijaykumar, "Multiplex: unifying conventional and speculative thread- level parallelism on a chip multiprocessor," in Proc. of Int'l Conference on Supercomputing, pp 368-380, June 2001.
32. J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy, "Introduction to the Cell multiprocessor," IBM Journal of Research and Development, Volume 49, Number 4/5, 2005.
33. Thomas Chen, Ram Raghavan, Jason Dale, Eiji Iwata, "Cell Broadband Engine Architecture and its first implementation: A performance view," 29 Nov 2005, http://www-28.ibm.com/developerworks/power/library/pa- cellperf/.
34. Timothy M. Pinkston and Jose Duato, "Appendix E: Interconnection Networks" in Computer Architecture: A Quantitative Approach, 4th Edition, by John L. Hennessy and David A Patterson, pp 1-114, Elsevier Publishers, 2007.
35. Mike Kistler, Michael Perrone, and Fabrizio Petøini, "Cell Microprocessor Communication Network: Built for Speed, " IBM Austin Research Lab, White Paper.
36. Mike Kistler, (Private Communication), IBM, Austin, TX, June 2006.
37. Scott Clark, (Private Communication), IBM, Rochester, MN, December 2005.
38. Scott Clark, (Private Communication), IBM, Rochester,MN, June/July 2006.
39. David Krolak, "Just like being there: Papers from the Fall Processor Forum 2005: Unleashing the Cell Broadband Engine Processor-The Element Interconnect Bus," November 29, 2005, http://www- 128.ibm.com/ developerworks/power/library/pa-fpfeib/.
40. Michael B. Taylor. "Scalar Operand Networks for Tiled Microprocessors," invited talk at the Workshop on On- and Off-chip Interconnection Networks, Stanford University, December 2006.
41. DeveloperWorks, IBM, "Meet the experts: The Mambo team on the IBM Full-System Simulator for the Cell Broadband Engine processor," 22 Nov 2005, http://www-128.ibm.com/developerworks/library/pa-expert7/.
42. DeveloperWorks, IBM, "An introduction to compiling for the Cell Broadband Engine Architecture," Parts 1-5, Part 1: 07 Feb 2006, http://www-128.ibm.com/developerworks/edu/pa-dw-pa-cbecompilel- i.html.
43. DeveloperWorks, IBM, "Just like being there: Papers from the Fall Processor Forum 2005: Unleashing the Cell Broadband Engine Processor: A programming model approach," 16 Nov 2005, http://www-128.ibm.com/ developerworks/libray/pa-fpfunleashing/.
44. DeveloperWorks, IBM, "Meet the experts: Alex Chow on Cell Broadband Engine programming models," 22 Nov 2005, http://www-128.ibm.com/ developerworks/librarv/pa- expert8/.
45. Vaidyanathan Srinivasan, Anand Santhanam, Madhaven Srinivasan, "Cell Broadband Engine processor DMA Engines, Part 1 : The little engines that move data,"06 Dec 2005, http://www-128.ibm.com/developerworks/power/library/pa- celldmas/.
46. DeveloperWorks, IBM, "Meet the experts: David Krolak on the Cell Broadband Engine EIB bus," 6 Dec 2005, http://www-128.ibm.com/ developerworks/power/library/pa.expert9/.