Efficient interconnects for clustered microarchitectures

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2002-January, Issue , 2002, Pages 291-300

  Parcerisa, J M ^a   Sahuquillo, J ^b   Gonzalez A ^a   Duato, J ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

Author keywords

Delay; Hardware; Logic; Microarchitecture; Multiprocessor interconnection networks; Network topology; Parallel architectures; Registers

Indexed keywords

COMPLEX NETWORKS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; ELECTRIC NETWORK TOPOLOGY; HARDWARE; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); MULTIPROCESSING SYSTEMS; NETWORK ARCHITECTURE; PARALLEL ARCHITECTURES;

DELAY; LOGIC; MICRO ARCHITECTURES; NETWORK TOPOLOGY; REGISTERS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84948777317     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2002.1106028     Document Type: Conference Paper

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