Trends toward on-chip networked microsystems

International Journal of High Performance Computing and Networking

Volumn 3, Issue 1, 2005, Pages 3-18

  Pinkston, Timothy Mark ^a   Shin, Jeonghee ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

interconnection network; microprocessor; microsystem; on chip network; partitioned architecture; system on chip

Indexed keywords

EID: 33746862216     PISSN: 17400562     EISSN: 17400570     Source Type: Journal    
DOI: 10.1504/IJHPCN.2005.007862     Document Type: Article

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52. In this paper, we restrict ourselves to microsystems built from CMOS technology as opposed to other more exotic nanotechnologies, e.g., MEMs, molecular and quantum computing technologies, etc.
53. Power consumption issues are not considered in this work. For more discussion on the impact of technology scaling and architectural techniques on power consumption, the interested reader is directed to Zyuban and Kogge (2000), Mudge (2001) and Wang et al. (2003).
54. The designation ‘FO4’ (or fan-out of four) is the delay (e.g., in picoseconds) of an inverter loaded by four identical inverters for a given technology.
55. Worst case environmental conditions of high temperature and low supply voltage were assumed.
56. The tile size in Table 1 is equivalent to that used in the Raw architecture (Taylor et al., 2002), which is 4 mm × 4 µm in 0.15 μm technology for 16 tiles per chip.
57. This processor architecture project was canceled before any chips were ever built.
58. We know of no hybrid designs that allow this as of yet, however these may emerge in the near future if the required logic complexity remains below the critical wire-limited bound.
59. For completion, also shown are some resources for communicating instructions for completion, but we focus on data communication.